R&D Engineering, Sr Staff Engineer - IP Verification Synopsys

8.0 - 9.0 years

8 - 9 Lacs

noida, uttar pradesh, india

On-site

The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/masters with good academic record. 7+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure.

Posted 1 day ago

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PCIe IP Design Verification Lead 7Rays Semiconductors India Private Limited

5.0 - 12.0 years

0 Lacs

karnataka

On-site

At 7Rays Semiconductors, we specialize in providing comprehensive VLSI design solutions to assist our clients in achieving excellence in execution. Our team of experts is highly skilled in various areas including architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation. We utilize the latest technologies and methodologies to deliver top-notch solutions tailored to meet our clients" specific needs. As a Design Verification Engineer specialized in protocols such as PCIe, CXL, and UCIE, you will be responsible for: - Demonstrating expertise in interconnect protocols such as PCIe, CXL, and UCIE. - Having a solid understanding of AXI/ACE/CHI protocols, with a particular emphasis on AXI. - Knowledge of DMA usage and its applications. - Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). - Experience in utilizing standard Verification IP (VIP) in Testbenches, preferably Synopsys tools. - Familiarity with AI/ML network concepts is considered beneficial. - Additional proficiency in perl/tcl scripting would be advantageous. The ideal candidate for this role should possess a Bachelor's Degree in Electrical, Electronics, or Computer Engineering, along with 5-12 years of relevant experience. If you are passionate about semiconductor design, eager to work in a collaborative environment, and committed to delivering high-quality solutions, we would love to hear from you.,

Posted 1 week ago

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