Senior Design Verification Engineer Capgemini Engineering

5.0 - 15.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Role: Design Verification Engineer Experience: 5 to 15 Years Location: Bengaluru Job Description: You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emph...

Posted 5 days ago

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ASIC Digital Design Engr, Sr II Synopsys Inc

6.0 - 10.0 years

0 Lacs

noida, uttar pradesh

On-site

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system lev...

Posted 3 months ago

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R&D Engineering, Staff Engineer - IP Verification Synopsys

7.0 - 12.0 years

3 - 12 Lacs

Delhi, India

On-site

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol funct...

Posted 5 months ago

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Staff Engineer, R&D Synopsys

5.0 - 10.0 years

4 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Requirements: Bachelors/masters with good academic record. 5+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a work exposure on any of the industry standard protocols like Jedec UFS, MIPI Unipro, MIPI MPHY, PCIe, USB, Ethernet, etc. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Leadership qualities to motivate and align team members towar...

Posted 5 months ago

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