ASIC Digital Design Engr, Sr II Synopsys Inc

6.0 - 10.0 years

0 Lacs

noida, uttar pradesh

On-site

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system levels, Test case coding and debugging, FC coding and analysis, and achieving quality metric goals and regression management. To be considered for this position, you should have a BS/BE in EE with 7+ years of relevant experience or an MS with 6+ years of relevant experience in IP cores verification and/or SOC verification. You should possess experience in developing HVL-based test environments, creating and implementing test plans, and extracting verification metrics like functional coverage. Additionally, you must have proficiency in HVL coding for Verification and hands-on experience with industry-standard simulators such as VCS, NC, MTI, along with relevant debugging tools. Exposure to verification methodologies like UVM/VMM/OVM is essential, and familiarity with HDLs such as Verilog and scripting languages like Perl is highly desired. A basic understanding of functional & code coverage, exposure to IP design and verification processes including VIP development, and good written and oral communication skills are crucial for this role. You should also be able to demonstrate strong analysis, debugging, problem-solving skills, and be self-driven. Join our Silicon IP business, where we focus on integrating more capabilities into an SoC faster. Synopsys offers the world's broadest portfolio of silicon IP, pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. We aim to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and bring differentiated products to market quickly with reduced risk. At Synopsys, we are at the forefront of innovations that reshape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our advanced technologies for chip design and software security power these breakthroughs. If you are passionate about innovation, we look forward to meeting you.,

Posted 2 months ago

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R&D Engineering, Staff Engineer - IP Verification Synopsys

7.0 - 12.0 years

3 - 12 Lacs

Delhi, India

On-site

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

Posted 3 months ago

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Staff Engineer, R&D Synopsys

5.0 - 10.0 years

4 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Requirements: Bachelors/masters with good academic record. 5+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a work exposure on any of the industry standard protocols like Jedec UFS, MIPI Unipro, MIPI MPHY, PCIe, USB, Ethernet, etc. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Leadership qualities to motivate and align team members towards business goals and priorities. As a motivator/leader of the R&D team in Synopsys, you will be responsible for Development and enhancements of features, flows and solutions Quality execution of VIP development, taking responsibility for designing, developing, debugging, creation of reliable plans and effort estimates for your projects. Focus on innovation to ensure continuous product enhancements

Posted 3 months ago

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