1.0 - 2.0 years

3 - 4 Lacs

hyderabad

Work from Office

Conduct classroom and online training sessions on VLSI design and verification. Teach HDL languages (Verilog, VHDL, SystemVerilog) and ASIC/FPGA design flows. Send Resume to : kalyangalactix@gmail.com Call : 7993047034 Provident fund

Posted 1 week ago

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Ams Verification Engineer Intverse It Solutions

4.0 - 8.0 years

14 - 24 Lacs

Bengaluru

Work from Office

Roles and Responsibilities Design verification using System Verilog, UVM, and SV/UVM methodologies. Experience with PrimeSim XA, WREAL, RNM, Verilog-A, and MIPI protocols. Proficiency in PCIe and USB 3 interfaces. Strong understanding of digital logic design principles and SoC architecture. Excellent problem-solving skills with attention to detail.

Posted 2 months ago

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