Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Senior Verifier - ASIC IP Cradlepoint

5.0 - 10.0 years

6 - 12 Lacs

Bengaluru, Karnataka, India

On-site

Cradlepoint is establishing a new Silicon R&D center in Bangalore, and we are looking for a Senior Verifier - ASIC IP to join our pioneering team. You will be instrumental in ensuring the quality and reliability of the IPs that power the digital ASICs for tomorrow's mobile standards, contributing directly to the advancement of 5G and 6G technologies. This role offers the opportunity to work with cutting-edge verification technologies within a collaborative and innovative global R&D environment. What We Offer: Creative Freedom: Immerse yourself in an an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package . What You Will Do: Key Responsibilities Take part in the verification of designs , whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments . Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans . Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies . Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects . Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Education: Bachelor's degree in electrical or computer engineering. Experience: 5+ years of industry experience in verification using SystemVerilog and UVM . Additional experience will allow placement at higher job levels. Strong Experience in/with: Development of verification test plans and creation of directed/randomized test cases . Formal verification . Implementing scoreboards, checkers, and bus functional models in an existing testbench environment. SystemVerilog Assertions . Additional Requirements: Experience with Cadence or Synopsys verification suites . Team-oriented , prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality . Strong focus on meeting project deadlines and deliverables . Proficient in English , with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification . Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), and issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs , especially AXI and CHI. ARM-based real-time microcontroller systems , including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces . Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.).

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