3 Verification Environment Jobs

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2.0 - 4.0 years

0 Lacs

noida, uttar pradesh, india

On-site

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

Posted 2 weeks ago

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3.0 - 7.0 years

0 Lacs

chennai, tamil nadu

On-site

As an FPGA expert with proficiency in Xilinx tools, you will be responsible for managing FPGA flows, including compilation, synthesis, debugging, performance optimization, and advanced feature implementation. Your expertise will be crucial in ensuring the smooth execution of projects involving FPGA technology. Additionally, you will demonstrate strong skills in Linting, Static Timing Analysis, Equivalence Checking, and Clock Domain Crossing, contributing to the overall efficiency and reliability of FPGA designs. Your hands-on experience with these aspects will play a vital role in meeting project requirements and delivering high-quality results. Furthermore, your role will involve developing...

Posted 1 month ago

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3.0 - 8.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this position should have 3 to 8 years of experience and be located in Bangalore. With 8-10 job openings available, the educational requirement is BE/B.Tech./MS/M.Tech. in Electronics or Electronics & Communication. Key Core Competencies include: - Experience in working on SoC level testbench and verification environment - Proficiency in testbench architecture, coding, and understanding of design issues in RTL - Ability to generate testbenches, create test vectors, conduct simulations, and perform gate-level simulations - Hands-on experience with System Verilog and Assertion-based verification methodology - Minimum 3 years of experience in High-Level Verification (HVL...

Posted 1 month ago

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