ASIC Design Verification Lead, Silicon Google

10.0 - 14.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, a minimum of 10 years of experience in creating and utilizing verification components and environments in standard verification methodology is required. Experience in verifying digital systems using standard IP components/interconnects such as microprocessor cores and hierarchical memory subsystems is also essential. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Candidates should also have experience in low-power design verification, as well as familiarity with Interconnect Protocols like AHB, AXI, ACE, CHI, CCIX, and CXL. Furthermore, expertise in Architectural backgrounds related to Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock, and Power Controllers is advantageous. As a member of the team, you will be involved in developing custom silicon solutions that drive Google's direct-to-consumer products. Your contributions will play a crucial role in shaping innovative products that are cherished by millions globally. Your skills and knowledge will influence the future of hardware experiences, ensuring exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining Google AI, Software, and Hardware expertise, our team creates groundbreaking experiences that are incredibly beneficial. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power. Our ultimate goal is to enhance people's lives through innovative technology solutions. Key Responsibilities: - Verify designs using advanced verification techniques and methodologies. - Collaborate across functions to troubleshoot failures and validate the functional accuracy of designs. - Develop comprehensive test plans encompassing verification strategy, environment, components, stimulus, checks, and coverage, ensuring user-friendly documentation. - Lead the verification of next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. - Collaborate with design engineers to debug tests and deliver functionally sound blocks and subsystems. Monitor coverage metrics to pinpoint verification gaps and demonstrate progress towards tape-out.,

Posted 2 weeks ago

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