3 Uvm Testbench Jobs

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10.0 - 15.0 years

10 - 15 Lacs

delhi, india

On-site

Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed test plan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to hel...

Posted 2 months ago

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5.0 - 9.0 years

5 - 9 Lacs

bengaluru, karnataka, india

On-site

Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed test plan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to hel...

Posted 2 months ago

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4.0 - 9.0 years

7 - 12 Lacs

Bengaluru, Karnataka, India

On-site

THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing o...

Posted 3 months ago

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