GFX sub-system/ Power Management verification Advanced Micro Devices, Inc

12.0 - 16.0 years

0 Lacs

hyderabad, telangana

On-site

As a Senior Silicon Design Engineer (SMTS) at AMD, you will be an integral part of the GFX sub-system (Graphics Power Management) verification team. Your role will involve collaborating with lead architects and block design teams to understand the features to be implemented and verified. You will be responsible for developing robust test plans for both synthetic and real workload trace, debugging verification test failures, and ensuring that the design meets functional, performance, and power expectations. To excel in this role, you must have a strong background in ASIC design and be proficient in debugging Verilog RTL code using simulation/emulation tools. Your analytical thinking and problem-solving skills, attention to detail, and ability to work effectively with diverse teams will be crucial for success. Additionally, having good English communication skills, both verbal and written, is essential. Preferred qualifications for this position include a minimum of 12 years of experience in ASIC verification, proficiency in Verilog, System Verilog, UVM methodologies, and C/C++ programming. A solid academic background with a B.E/B.Tech or M.E/M.Tech degree in ECE/Electrical Engineering/Computer Engineering with Digital Systems/VLSI as a major is required. Candidates with graphics pipeline experience and deep knowledge of computer architecture will be given preference. Being a self-starter who can independently drive tasks to completion, while also possessing strong teamwork and interpersonal skills, is essential for this role. This position is based in Hyderabad, India. If you are looking to be part of a dynamic team that is dedicated to pushing the limits of innovation and solving the world's most important challenges, then AMD is the place for you. Join us in advancing technology and making a meaningful impact in the industry, communities, and the world.,

Posted 1 week ago

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ASIC Verification Engineer- Staff Synopsys

6.0 - 12.0 years

6 - 12 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks - Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones leadership skills. Key Qualifications and Experience Must have BSEE/ MSEE in EE with 6 to 12 years of relevant experience in the following areas: Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus. Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts. Exposure to quality processes in the context of IP design and verification is an added advantage In addition, the candidate should have good communication skills, will be a team player, and will have good problem-solving skills.

Posted 2 months ago

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