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5.0 - 9.0 years
0 Lacs
karnataka
On-site
Role Overview: At Synopsys, you will be driving innovations that shape the way we live and connect, leading in chip design, verification, and IP integration to empower the creation of high-performance silicon chips and software content. As an experienced ASIC Digital Verification Engineer, you will play a crucial role in ensuring the highest quality in digital design, leveraging your expertise in verification methodologies and advanced tools to deliver innovative solutions. Key Responsibilities: - Design and implement verification environments for Interface IP protocols - Create and execute detailed test plans for complex ASIC designs - Develop and maintain verification IP and testbenches us...
Posted 13 hours ago
0.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Responsibilities Job Description : Verification of Mixed-Signal designs at chip and module level. Analog/Mixed-Signal self-checking simulation. Implementation of analog models in Verilog-/VHDL-AMS to speed up AMS simulation. Application of metric-driven Verification (MDV) methodologies. Development and tracking of Verification plans. Integration of Verification-IP. Measurement and analysis of regression results. Cooperate on evaluation of silicon, test correlation, and scripting (Perl, Python, C++). Work with verification team on verification plans, test cases, and analyzing test results . Very good experience in Verilog AMS , Verilog-A, WREAL, modelling of analog blocks. Very good experienc...
Posted 20 hours ago
6.0 - 9.0 years
0 Lacs
hyderabad, telangana, india
On-site
BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills
Posted 3 days ago
15.0 - 17.0 years
0 Lacs
bengaluru, karnataka, india
On-site
I hope you are doing well! My name is Uma from the TA team at Harman, and I&aposm reaching out to you today to briefly introduce myself as well as personally extend this invitation to you on behalf of my company. Currently, we are looking to identify/invite exceptional talent like yourself, to join our Technical team at Harman. About the Company Harman is a leading company in the technology sector, dedicated to innovation and excellence in our products and services. About the Role In this role, you will be interacting directly with potential customers and teams to gather requirements, estimate effort, cost, schedules, design size and feasibility. Responsibilities You will also be planning RT...
Posted 3 weeks ago
15.0 - 19.0 years
0 Lacs
karnataka
On-site
As a member of the Technical team at Harman, you will play a crucial role in interacting with potential customers and teams to gather requirements, estimate effort, cost, schedules, design size, and feasibility. Your responsibilities will also include planning RTL logic design and verification projects, mentoring junior engineers, and ensuring successful project outcomes through collaboration with implementation teams. Key Responsibilities: - Plan RTL logic design and verification projects, including initial synthesis with constraints and UPF development. - Direct project technical teams, mentor junior engineers, and interact with implementation teams for successful project outcomes. - Work ...
Posted 4 weeks ago
12.0 - 16.0 years
0 Lacs
hyderabad, telangana
On-site
As a Senior Silicon Design Engineer (SMTS) at AMD, you will be an integral part of the GFX sub-system (Graphics Power Management) verification team. Your role will involve collaborating with lead architects and block design teams to understand the features to be implemented and verified. You will be responsible for developing robust test plans for both synthetic and real workload trace, debugging verification test failures, and ensuring that the design meets functional, performance, and power expectations. To excel in this role, you must have a strong background in ASIC design and be proficient in debugging Verilog RTL code using simulation/emulation tools. Your analytical thinking and probl...
Posted 2 months ago
6.0 - 12.0 years
6 - 12 Lacs
Bengaluru / Bangalore, Karnataka, India
On-site
Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks - Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract probl...
Posted 4 months ago
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