2115 Uvm Jobs - Page 46

Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe and CXL Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies This is a Full Time position Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles Responsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated ...

Responsibilities Be the primary point of contact for IP and SoC functional verification for cross-functional teams. Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs. Develop high-performance and low power hardware to enable Google's continuous innovations in consumer hardware. Minimum qualifications: Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience. 5 years of experience in driving/leading functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs). Experience working with System Verilog and Universal Verification Methodology...

Role Responsibilities: Plan and develop formal verification strategies for complex digital design blocks. Create properties and constraints using formal verification tools for property verification. Resolve verification challenges and improve methodologies for better results. Architect and implement reusable components to enhance formal verification processes. Job Requirements: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and System Verilog. Experience with designing and maintaining verification test benches and environments.

Role Responsibilities: Verify complex digital design blocks (e.g., GPU, CPU, Image processors) by analyzing design specifications and working with design engineers. Create and enhance constrained-random verification environments using SystemVerilog, UVM, or formal verification techniques with SystemVerilog Assertions (SVA). Write coverage measures for stimulus and corner cases, ensuring thorough testing of the design. Debug tests in collaboration with design engineers to ensure functional correctness and close coverage gaps before tape-out. Job Requirements: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience. 3 year...

You will be responsible for leading the verification efforts for complex System on Chips (SoCs) and multi-chiplet System on Packages at Krutrim. This includes developing verification plans, testbench environments, and reusable verification IP. You will work on module, sub-systems, chiplets, and complex multi-chiplet testbench environments. Additionally, you will be involved in developing UVM and C/Python based testbench environments for functional, netlist, and power simulations. You will also contribute to developing reference models using System Verilog/SystemC/Python and improving verification flow and methodology. Debugging design units using simulation and formal tools and methodologies...

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the projec...

As the owner of Ethernovia's India digital hardware team, you will be responsible for all aspects of digital design and digital verification. This position requires both hands-on technical contribution as well as managerial and technical leadership. You will hire and build your own team to plan and execute the design, verification, and validation of advanced automotive communication semiconductors and systems. Key Qualifications: - BS and/or MS in Electrical Engineering, Computer Science, or related field - Minimum 15+ years combined of ASIC design, verification, and leadership experience - Strong understanding of ASIC design and verification fundamentals and industry standard methodologies ...

Cadence Design Systems is seeking a Lead Hardware Engineer for their DFT IP R&D team in Noida with 4-6 years of experience. As a member of the R&D staff, you will be working on Cadence's MODUS DFT software solution, a comprehensive product designed to achieve high coverage, reduced test time, and superior PPA. We are looking for candidates with expertise in various areas such as RTL design, DFT architecture, verification, power analysis, and optimization. This role involves developing cutting-edge DFT tools, designing and verifying RTL and test benches, and providing support to application and product engineers. You will be part of a team responsible for creating innovative technologies in t...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention...

Dear Candidate , Greeting from HCL Tech!!!!!!! We have come across your profile in Portal. Please Ignore if you already shared or submitted Details or Applied. As its a default retrigger. We are hiring on below Design Verification Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. JD - Design Verification Engineer - Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logi...

Verification Engineer Location: Bengaluru Experience: 3+ Years Employment Type: Full-time Job Responsibilities: Create and carry out detailed plans to verify SoC systems. Design and manage test benches using SystemVerilog and UVM. Test the functionality, performance, and low-power aspects of designs. Identify and fix any design or verification problems on your own. Work with high-speed communication protocols like AXI, PCIe, Ethernet, CXL, and UCIe. Make sure that the design is thoroughly tested and follows the specifications. Skills Required: At least 3 years of experience in verifying SoC systems. Strong knowledge of SystemVerilog, UVM, and scripting languages like Python or Perl. Experien...

Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsy...

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact ...

We are hiring on below Design Verification Engineer/ RTL Design Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. Job Descriptions : Please specify for which role your application is for - DV/RTL JD - Design Verification Engineer - Engineer/Lead/Senior Lead JD - RTL Design Engineer- Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and ...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Verification of processor-based subsystem ...

Role - Micro Loan Officer - Field Officer Reporting To Branch Manager 1. Starting business in a new village a. Village identification within the radius b. Feasibility study of the village based on demographics, activities and financial needs ofthe customers c. Assist the MC-IC in making the village approval 2. Sourcing of business a. Identification of customers and forming of Joint Liability Groups b. Filling up of the application form c. Verification of the residence and business of the customer d. KYC verification e. Pre-disbursement training f. Visiting potential customers in order to develop business 3. Disbursements a. Collection of KYC documents b. Assisting the MC-IC for disbursement ...

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure su...

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience i...

SR. VERIFICATION ENGINEER – SOC VERIFICATION SmartSoC is looking for smart and enterprising SOC Verification experts to come and work on complex SOC Verification projects. This role will include- Technical execution of SOC Verification projects of complex ARM based SOCs Test Planning, Environment Architecture, SV-UVM environments Desired Skills and Experience- 3 – 10 years experience in Design Verification Excellent Communication and Presentation Skills Expert Knowledge in SOC Verification Expert at Verification – Coverage Driven Test Planning, Architecting Environments, Verification Flow Strong knowledge in System Verilog Knowledge in at least one methodology, OVM, UVM, VMM or RVM Very Good...

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experie...

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Ma...

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/Sys...

1-3 years of experience in RTL DFT Verification (DFx). Good Understanding of JTAG IEEE-1149.1 and IJTAG IEEE P1687 standard. Understanding of using ICL and PDL files for verification and knows to create a testbench. Experience in JTAG RTL verification within any UVM. Able to debug simulation fails effectively utilizing debug tools like Synopsis Verdi. Basics of system Verilog, Basics of UVM, and preferably System Verilog assertions Scripting knowledge of TCL/Perl. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral mode...

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). P...