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4.0 - 9.0 years

15 - 30 Lacs

Kochi

Hybrid

Greeting with HCL Tech! We were looking somebody who is having experience in Design Verification Experience: 4 to 10 Years Location: Kochi Job Description: General verification expertise System Verilog. UVM Understanding of ARM processor based SOCs, AXI / AHB Good knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug) Strong hands on work experience of test development, simulation along with usage of popular EDA tools Good debug skills – Check that engineer has done reasonable amount of debug in past projects Has logical and methodical approach to debug issues /failures Has used standard tools for debugging, as applicable

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2.0 - 5.0 years

3 - 7 Lacs

Bengaluru

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As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

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7.0 - 12.0 years

14 - 19 Lacs

Bengaluru

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Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch. Maintain and improve existing DV environments. Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications Bachelors Degree or equivalent experience in EE, CE, or other related field. 7+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying sophisticated blocks, clusters and top level for ASIC. Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Masters Degree in EE or CE with 5+ years of relevant work experience. Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

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1.0 - 6.0 years

6 - 15 Lacs

Hyderabad, Chennai, Bengaluru

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Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

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5.0 - 10.0 years

7 - 12 Lacs

Bengaluru

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ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

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4.0 - 9.0 years

7 - 13 Lacs

Hyderabad, Bengaluru

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Key Responsibilities: Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IPs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IPs and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Strong understanding of Coherency rules in ACE and ACE5 Experience with architecting BFMs/VIPs Should be able to handle a team of 3-4 engineers (for senior position). IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level as per the requirements Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification Strong in SV and UVM. PCIe Gen5 Tetsbench development experience is required. CXL2.0/3.0 protocol working experience will be added advantage Skills and Qualifications: Education: B.Tech/B.E. or M.Tech/M.S. in Electronics, Electrical Engineering, or a related field. Experience: 3-14 years of hands-on experience in ASIC design verification. Tools & Technologies: Proficiency in hardware description languages (Verilog, VHDL, System Verilog). Familiarity with UVM (Universal Verification Methodology) and other verification methodologies. Experience with simulation and debugging tools (ModelSim, VCS, Questa). Knowledge of scripting languages (Python, Tcl, Perl) for test automation. Experience with version control tools such as Git or SVN. Familiarity with formal verification tools and techniques is a plus. Desired Skills: Strong understanding of digital logic design, state machines, and timing analysis. Ability to work independently and collaboratively within a team environment. Strong problem-solving and analytical skills. Good communication skills to effectively report verification results and progress. Preferred Qualifications: Experience with high-level synthesis tools. Knowledge of low-power design techniques. Familiarity with performance verification and hardware-software co-verification.

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2.0 - 6.0 years

4 - 8 Lacs

Bengaluru

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Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

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4.0 - 9.0 years

6 - 10 Lacs

Bengaluru

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As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

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4.0 - 8.0 years

18 - 30 Lacs

Hyderabad, Bengaluru

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Strong knowledge in SV,UVM Skills: SOC/IP Verification Protocol: Ethernet/PCIe Experience: 4+ Years Should have Scripting knowledge Need experience in 2 tape outs projects

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2.0 - 7.0 years

5 - 15 Lacs

Noida, Bengaluru

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Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. Prepare, update, and structure course materials and assignments as per industry standards.

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8.0 - 13.0 years

10 - 15 Lacs

Bengaluru

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Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Job Description ASIC Verification Lead Summary of the offer: Integrating ASIC functional verification team. ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main responsibilities: Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams. Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications. Write and perform closely test plans with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C ++ Monitor, analyze and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects. Skills: Participated in the successful verification of a complex SoC or ASIC. Mastering UVM or equivalent verification methodology. Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Strong knowledge of simulation tools and coverage database visualization tools Developed test plans that helped identifying sharp functional defects. efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints Experienced in improving processes and methodologies Experience in managing tasks for a small team. Required minimum experience: 7 years Required minimum studies: Master/Engineer in Electronics and Communication Engineering.

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0.0 - 1.0 years

1 - 2 Lacs

Bengaluru

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Designation: Technical Support Engineer - VLSI Experience : 0-1 Years Education : B.tech/ BE- or M.Tech VLSI. ECE/ Diploma in Mechatronics/ECE Industry Type: Education / E-Learning / Semiconductor Category: Technical Job Description Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Desired Candidate Profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. For more details, kindly contact 7406043555, fiza@maven-silicon.com

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4.0 - 9.0 years

16 - 31 Lacs

Hyderabad, Chennai, Bengaluru

Work from Office

1.Must Have: SoC or IP 2.Experience Languages : System Verilog (must) 3.Methodologies: OVM/UVM/VMM 4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI 5.Processor/ARM Based SoC Verification experience 6.Candidate must have expertise in System Verilog. 7.Experience in ARM base SoC Verification 8.Strong Analytical skills desirable if having worked.

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10.0 years

0 - 0 Lacs

Bengaluru

Work from Office

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineers DDR (either IP or SoC level experience) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own functional coverage, regression setup, and closure. Integrate DDR models, controllers, PHYs, and validate their interactions. Debug and resolve simulation failures and functional issues. Drive code and functional coverage improvements to ensure thorough verification. Lead or participate in technical reviews and mentor junior engineers. Required Skills & Experience: 10+ years of hands-on experience in ASIC/IP/SoC verification. Strong expertise in SystemVerilog, UVM, and functional coverage methodology. In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols. Experience with DDR controllers, PHY integration, and JEDEC standards. Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc. Good scripting skills in Python, Perl, or Shell for automation and regression management. Excellent debugging and problem-solving skills. Familiarity with AXI/AHB protocols and interconnects is a plus. Experience working with memory models and timing analysis. Preferred Qualifications: Experience with post-silicon validation or DDR hardware bring-up. Knowledge of formal verification tools and techniques. Experience with low power verification and timing closure tools. TekWissen Group is an equal opportunity employer supporting workforce diversity.

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2.0 - 7.0 years

30 - 35 Lacs

Bengaluru

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Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as we'll as analyzing functional coverage results to guarantee zero defect outcomes. You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 2+ years experience in constrained-random, coverage driven verification environments. Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations.

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15.0 - 16.0 years

50 - 60 Lacs

Bengaluru

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Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

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5.0 - 10.0 years

14 - 18 Lacs

Bengaluru

Work from Office

Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Job Description Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques Implementing functional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as we'll as analyzing functional coverage results to guarantee zero defect outcomes. You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 5+ years experience in constrained-random, coverage driven verification environments. Experience in RAL Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations.

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8.0 - 12.0 years

0 - 0 Lacs

Bengaluru

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Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineers PCIe (either IP or SoC level experience) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs. Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in SystemVerilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, SimVision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers TekWissen Group is an equal opportunity employer supporting workforce diversity.

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5.0 - 10.0 years

4 - 8 Lacs

Bengaluru

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Position: Design Verification Engineer Location: Bangalore Experience: 5+ Years Key Skills Required: Strong experience in CXL or PCIe Protocol Verification Proficiency in UVM, SystemVerilog, Verilog Hands-on experience with simulation tools (VCS, ModelSim, Questa, etc.) Excellent debugging and problem-solving skills Good to Have: Exposure to AMBA protocols (AXI, AHB, APB) Knowledge of scripting languages like Python or Perl Educational Qualification: Bachelor s or Master s degree in Electronics Engineering , Electrical Engineering , or related field

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8.0 - 13.0 years

10 - 11 Lacs

Bengaluru

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Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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8.0 - 13.0 years

12 - 17 Lacs

Bengaluru

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Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired .

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3.0 - 7.0 years

7 - 10 Lacs

Bengaluru

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Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

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0.0 - 1.0 years

1 - 2 Lacs

Bengaluru

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Hiring for Freshers Desingnation:- Technical Support Engineer - VLSI Work Mode: WFO (6 days) No.of positions: 10 Experience: 0 - 1 years Education: BE/BTech/MTech/ECE/EEE in VLSI Industry Type: Education / E-Learning / Semiconductor Filter: Full- time- Work from Office Stipend: 15k - 20k Role & responsibilities Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics.

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0.0 years

1 - 2 Lacs

Bengaluru

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3 years Service Agreement - Freshers Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.

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1.0 - 4.0 years

2 - 5 Lacs

Bengaluru

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Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Posted 2 months ago

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