Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Principal Duties & Responsibilities Responsible for creation of "State of the art" UVM based verification test benches and methodologies to verify complex IP"™s and Sub-Systems. Define testplans, tests and verification infrastructure for modules, clusters and systems. Exposure to Power Aware Verification will be a plus. Build efficient and reusable bus functional models, monitors, checkers and scoreboards. Implement Functional coverage and own verification closure. Work with architects, designers, emulation and post silicon teams verification completeness. Good debugging & analytical skills. "¢ Applies advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry independently; has a basic understanding of other domains. "¢ Reads device specification sheets and interprets complex details required to design various hardware features; provides guidance to less experienced engineers working with spec sheets. "¢ Identifies advanced ways to optimize tests and/or hardware designs by evaluating device performance over a wide range of operating conditions and configurations. "¢ Evaluates complex design features to identify potential flaws (electrical, mechanical, hardware), compatibility issues, and/or compliance issues; advises less experienced engineers on design evaluations. "¢ Documents complex details about materials, components, chipsets, and functionality for a device while being mindful of potential compatibility, safety, and compliance issues; assists less experienced engineers in their documentation of these details. "¢ Troubleshoots advanced issues with product designs and finds solutions that are documented and shared with internal teams working on similar products. "¢ Provides essential technical input, support, and documentation for internal customers; advises less experienced engineers on how to provide support for clients. "¢ Acts as a tech lead on mid-sized to large projects and owns the outcome of the project. "¢ Manages project-related activities (e.g., meetings, documentation, deliverables) between their team and other teams working on the same or similar products, operating across locations and time zones; brings the project to conclusion. "¢ Utilizes deep understanding of Qualcomm products to evaluate and test hardware designs and identify unique components or functions that could potentially be filed for IP patents; shares these findings with their manager. "¢ Displays deep knowledge in a specific area; acquires advanced knowledge of industry trends, competitor products, and advances in various engineering fields from publically available information; shares knowledge with others on team and helps less experienced engineers understand and apply advanced concepts. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

BA Payments Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Location :Chennai ,Bangalore ,Pune Grade :C1&C2. NP :60 days Max.

Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Preferred Qualifications 5+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Interested can share resume on Shubhanshi@incise.in

Functional Verification Engineer AMD Hyderabad Must have hands on experience coding In System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience working on subsystem or SoC level would be helpful. Candidate should be proactive in communication. Developing and maintaining block level test benches. Vplan, regression and coverage closure Work on testbenches with real number modelling. Netlist and Gate level simulations. Must be able to work independently to self-manage to deliverable as per the schedules

Job Description Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for ISCP client projects. This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Bangalore, India. As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing. Your influence will cross organizational boundaries with our manufacturing and validation partners. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools. Qualifications The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : UVM, AMBA protocols, system verilog, IP sub-system DV. Other technical requirements: 3 to 8 years of relevant pre-silicon verification/logic design experience. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation. Experienced in Power-aware design and validation flows. Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job Description Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for ISCP client projects. This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Bangalore, India. As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing. Your influence will cross organizational boundaries with our manufacturing and validation partners. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools. Qualifications The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : UVM, AMBA protocols, system verilog, IP sub-system DV. Other technical requirements: 3 to 8 years of relevant pre-silicon verification/logic design experience. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation. Experienced in Power-aware design and validation flows. Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD. The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content. K EY RESPONSIBLITIES : Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs. Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY. Use the performance-power-reliability trade off matrix to achieve IP goals. Define the appropriate margining methodology and scope for data, clock and async timing paths. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes. Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes. Provide technical guidance to junior team members. Use scripting skills to meet efficiency and quality goals across all timing workflows. P REFERRED EXPERIENCE : 12+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Experience with SerDes or DDR PHY digital logic layer implementation is required. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop analysis. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints. Proficient in AMS design flows, tools and methodologies. Experience in evaluating and adopting new tools and methodologies to improve design processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the enhancement and evolution of GPU verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification reviews, suggesting improvements where necessary. About you Committed to making your customers, stakeholders and colleagues successful, you re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You\u0027ll have: Demonstrated experience in developing verification environments for complex RTL designs. Strong understanding of constrained-random verification methodologies and the challenges of achieving verification closure. Ability to define verification requirements, determine implementation approaches, and design testbenches. Expertise in root-cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. Experience managing multiple projects simultaneously. Strong communication skills for effectively conveying technical issues, both verbally and in writing. You might also have: Experience leading teams. Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Understanding of functional safety standards such as ISO26262

Put in dedicated effort to understand graphics concepts and enhance your verification expertise. Collaborate effectively within a team, demonstrating a willingness to learn and contribute. Take ownership of your tasks by planning, estimating, and tracking your progress. Assist in developing tests, sequences, checkers, scoreboards, and other components in UVM. About you Committed to making your customers, stakeholders and colleagues successful, you re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You\u0027ll have: Strong expertise in Digital Circuits and Verilog. Proficient in SystemVerilog and UVM, with a strong desire to further enhance skills in these areas. You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++

Design verification plans and develop, maintain UVM testbench components. Gain a deep understanding of the design and testbench under your responsibility. Build UVM testbenches, including writing tests, sequences, checkers, scoreboards, and verification/coverage plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the improvement and evolution of GPU verification methodologies. Take ownership of coverage closure and provide verification metric reports. About you You\u0027ll have: Experience in developing and maintaining verification components. Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies. Skilled in debugging and identifying root causes of issues. Effective communication of technical issues, both verbally and in writing. You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++

About The Role : The main responsibilities of the job includes: Define, develop, and perform functional validation for GPUs in post-silicon environment, focusing on validation of PCIe in the context of discrete GPU. The job requires: Ability to capture analyzer traces and debug, ability to use exerciser for compliance. Ability to debug CV5 compliance issues. Ability to understand high-level spec and correspondingly develop test plan, test content and debug scripts, etc. Driving PO execution and debugs. Familiarity with compliance workshop and ability to debug issues across multiple hosts. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 6+ years of industry experience The years of experience mentioned above must include: PCIe post-silicon validation. Debugging PCIe functional and compliance issues Preferred Qualifications: Experience in driving post-silicon validation as technical lead Experience in GPU post-silicon validation Experience in engaging activities in compliance workshop. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience. Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB, I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Position: Staff Engineer - System C Modeling Experience: 6 to 10 yrs Job Location: Bangalore Job Type: Permanent & Day Shift Qualification: B.Tech / B.E / M.Tech / M.E Responsibilities: Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Experience: 5 to 8 Years of experience in the following areas: - Functional Modeling & Verification: Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage - Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic - Languages Expertise: C, C++, Python, System C, System Verilog/UVM will be a plus - Tool Expertise: Visual Studio , Git, Bitbucket Education & Soft Skills: Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background Strong Problem Solving Efficient Communication Team Leading & Mentoring skills Kindly Note: Candidates who cannot relocate to Bangalore, are not preferred to apply. We are looking for candidates who can join 15 to 30 days notice. Interested candidates please feel free to reach out Ravindra @ 8340937197 or Please email your profile to: ravindra.m@creenosolutions.com

General Summary: The role generally entails a mixture of: Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas: - Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/ AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/ Analog/ RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm SoC Verification Engineer The candidate will be responsible to own SoC Interconnect DV (Connectivity matrix, Coherency, Clock gating, Performance etc) during the project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets / Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI. Solid hands-on working experience on System Verilog and UVM methodology. Expert in handling protocol BFM/ VIP integration and traffic sequence development. Experience in coding assertions and functional coverage bins. Qualcomm Power DV Engineer We are looking for passionate, highly motivated, and creative individuals to be part of our Power Verification team. As the power team member, you will work on projects that will define the next generation of Modem, Mobile, XR/VR and Automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's, cutting edge power optimization techniques, Functional safety aspects and many other leading technologies deployed in our Snapdragon chips. General Summary Qualcomm Power DV team is responsible for the verification of Power Controller sub-system that powers up/controls the clock/voltage/ operating level/power for the entire SoC. Along with the complex power controllers, the team is responsible for verification of various sensors and the respective controllers, Power limits management IPs and the IPs interacts with the external PMIC. In the role of Power Verification Engineer, you are expected to understand the Low power design functionality and verification strategies and driver the overall SoC low power verification. The Responsibilities Will Majorly Include Understanding of SoC power domains and HW programming guide sequences Develop test plan to verify all low power aspects across all modes of verification RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Participate in post Si debug and bring-up activities Exploring innovative dynamic or static methodologies by engaging with EDA vendors Work with architects, designers, FPGA and post-silicon teams to ensure that the IPs are verified/validated thoroughly. Preferred Qualifications: Strong System Verilog/ UVM based verification skills & Experience with Assertion & coverage-based verification methodology Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Bus protocols (AHB/ AXI/APB) C/C++ with any ARM core knowledge Exposure to Formal/Static verification methodologies and Post-Si debugs would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization BTech/MTech with below years of experience in verification closure of complex Unit, Sub-system or SOC level verification. 5 To 12 Years of experience to lead Power DV of one or more SoCs Qualcomm SOC DV Engineer (MM) As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.Minimum qualifications BE/BS degree in Electrical Engineering with 5+ years of practical experience Strong fundamentals in digital ASIC verification Experience in IP/SS/ SoC level verification of medium to high complexity design Knowledge of one or more of Multimedia design blocks such as Display/ Camera/Video/GFx Familiarity with system level HW and SW Debug techniques and Verification requirements Preferred qualifications MS degree in Electrical Engineering; 4+ years of practical experience Expertise in IP/SS/System level verification flows of one or more of Multimedia design blocks Familiarity with one or more of the bus standard interface protocols for Multimedia designs, such as DisplayPort/ HDMI/ CSI/DSI Exposure to ARM Core debugging techniques would be a plus Strong understanding of AMBA bus protocols A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Extensive knowledge in multiple testbench structures Exposure to FPGA and emulation platform debugs Proficiency in UVM, C/C++ Experience w/ PSS or higher-level test construction languages is an added advantage Knowledge of assertion-based formal verification is an added advantage Additional Job Description Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Debug test cases and report verification result to achieve expected code/functional coverage goal Assist in silicon bring-up, debug and characterization Qualcomm SOC Verification Engineer (Debug) As verification engineer candidate will be responsible to own SoC Debug DV (Crash reset, Trace, debug infra etc) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets/Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Working knowledge and design understanding of Debug architecture of a SoC which includes Crash flow, JTAG, Trace, triggers, monitors, Scandump etc. Exposure to Power aware simulations and Gate Level simulations Good understanding of processor based Soc level verification which includes Verilog, System Verilog and UVM based environment. Good understanding of AHB/AXI & ATB-AMBA protocol.

Must have expertise in ASIC viterification methodologies and ASIC design flow Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects Experience in any of the listed topics: UVM, formal verification, mixed-signal simulations, power-aware simulations Experience in setting up and debugging functional and/or gate-level simulations Experience in translating functional requirements into verification plans Experience in developing verification environment and regression setup. Coverage analysis and closure

Job Description : Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience.

POSITION SUMMARY The candidate should have direct and first-hand experience working in managing 4 -10 member engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements). ROLE & RESPONSIBILITIES Incumbent will be responsible for Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customers products Incumbent will lead of an IP Verification team and provide technical leadership to the Design Verification team as a whole To lead a team of 10-13 engineers Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Must lead management and customer reviews for multiple projects The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective. Develop/modify scripts to automate the verification process. Maintain and extend assertion libraries, including support for both simulation and FV. Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan ESSENTIAL SKILLS & EXPERIENCE Minimum 6 years of experience in System Verilog HVL. Minimum 6 year of experience in OVM/UVM/VMM/Test Harness. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at-least 2 to 3 SoC Verification projects Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. Review and Audit participation. At-least 3 years of experience in handling team of 5 to 10 engineers. Define/derive Scope, Estimation, Schedule and Deliverables of proposed work. Assure compatibility of resources, tools, platform Work with customers through acceptance of deliverables. Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Please note that this is a Work from Office Job and incumbent must have willingness and experience of leading and mentoring junior engineers. EDUCATION BACKGROUND B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Additional About The Role : As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need: BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience: MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areas:Microprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

• Proficient in CPU architecture (ARM knowledge is desirable), Verilog, SystemVerilog and possess strong debugging skills. • Experience on CPU unit/microarchitecture verification • Should have worked on complex coverage driven verification projects Required Candidate profile • Experience - 8-15 Years • Experience of collaborating with cross-functional teams

Analog Circuit Design Circuit Design implementation of SERDES blocks like Transmitter, FFE, Receiver, CTLE, DFE, Summer, SAL/Design of basic analog IPs like ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor etc/Design of blocks like LDOs, Band Gap reference, Current Generators, POR. Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do Conduct verification of the module/ IP functionality and provide customer support Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology Create test bench development and test case coding of the one or multiple module Write the codes or check the code as required Execute the test cases and debug the test cases if required Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed Test the entire IP functionality under regression testing and complete the documentation to publish to client Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency Write scripts for the IP Comply with project plans and industry standards Ensure reporting & documentation for the client Ensure weekly, monthly status reports for the clients as per requirements Maintain documents and create a repository of all design changes, recommendations etc Maintain time-sheets for the clients Providing written knowledge transfer/ history of the project Stakeholder Interaction Stakeholder Type Stakeholder Identification Purpose of Interaction Internal Tech Lead/ Architect/ Product Owner Regular reporting & updates, testing and debugging etc. External Client technical team (Product Owner, Engineering Manager, Scrum Master) Scripts of test cases, escalations etc Display Lists the competencies required to perform this role effectively: Functional Competencies/ Skill Leveraging Technology - Knowledge of current and upcoming technology along with expertise in programming (automation, tools and systems) to build efficiencies and effectiveness in own function/ Client organization - Competent Process Excellence - Ability to follow the standards and norms to produce consistent results, provide effective control and reduction of risk - Expert Domain knowledge - Industry knowledge as per the project requirement and industry standards of various processes - Competent Technical Knowledge - Knowledge of System Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL) - Competent to Expert Competency Levels Foundation Knowledgeable about the competency requirements. Demonstrates (in parts) frequently with minimal support and guidance. Competent Consistently demonstrates the full range of the competency without guidance. Extends the competency to difficult and unknown situations as well. Expert Applies the competency in all situations and is serves as a guide to others as well. Master Coaches others and builds organizational capability in the competency area. Serves as a key resource for that competency and is recognised within the entire organization. Behavioral Competencies Process Orientation Innovation Managing Complexity Client centricity Execution Excellence Passion for Results Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 3. Self-development Skill test for next level clearance on Trend Nxt

Wipro Limited (NYSE:WIT, BSE:507685, NSE:WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSE:WIT, BSE:507685, NSE:WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.