Job Description In your new role you will: Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the"Universal Verification Methodology" (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using SystemVerilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs; Your Profile You are best equipped for this task if you have: You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) -experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Job Description In your new role you will: Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the"Universal Verification Methodology" (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using SystemVerilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs; Your Profile You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) -experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Masters/Bachelors in Electrical Engineering or Computer Science with 5-12 years of relevant work experience. Execute SoC Digital/Mixed Signal verification tasks and work closelywith team members to review and understand the relevant functional andsafety-related requirements. In your new role you will: Write verification plans to meet these requirements after closealignment with other verification teams for proper work split accordingto mutually acceptable verification assignment. Execute the verification plan by developing C/C++ test cases andSystem Verilog/UVM test bench components and by integrating 3rd partyVIP components. Simulate and debug at RTL, Unit Delay, and Gate Level usingappropriate tools and flows including Emulator, Portable Stimulus, orFormal methodologies for functional and toggle coverage closure. Lead a team technically through exploring new environment andidentifying potential enhancement areas through new methodology. Identify and setting mid/long term goals based on benchmarking againstindustry standards. You are best equipped for this task if you have: Understand the usage of tools like Xcelium, Spectre(X) and Simvision Strong foundational knowledge of digital/mixed-signal design &verification. Knowledge and hands-on experience of System Verilog and UVM. Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes Self-motivated, flexible and with strong interpersonal skills Good communication with interpersonal skills and is a good team playerwho is able to work well with both internal and external partners. Candidate who has more relevant working experience will be consideredfor a more senior position. It is a plus to have: Hands-on experience in hardware-software debugging at the system orapplication level. Hand-on experience with gate-level-simulations and withdebugging/troubleshooting skills is a plus Understanding of UPF context of analog/transistor level Basic analog knowledge for debugging purposes. Experience in automotive industry in Functional Safety ISO26262 andCybersecurity ISO21434 are advantageous. Contact: Jyoti.Vimal@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys : XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating problem solving mindset Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches You are best equipped for this task if you have: Bachelors with 9+ years of experience Mentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture. Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilo g-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Job Description In your new role you will: Will be part of a team that handles Verification for complex SoCs and close the Verification to the challenging milestones. SoC Verification: Full-chip VR creation as per the chip requirements and UVM/OVM Test benches creation Support in building verification infrastructure at the chip level asper the requirements Capable of handling multiple areas of SoC Verification: RTL, Power Aware and Gate Level Verificatio n Your Profile You are best equipped for this task if you have: Bachelors - 6 to 7 years experience, Master s - 5 to 6 years experience Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/ System Verilog and UVM . Experience and knowledge in V erification of SoCs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements well and good knowledge in industry standard protocols is a plus Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the "Universal Verification Methodology" (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management. Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Senior Staff Chip Verification Engineer Job Description In your new role you will: Lead a team technically through exploring new environment and identifying potential enhancement areas through new methodology. Identify and setting mid/long term goals based on benchmarking against industry standards.">Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements. Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment. Execute the verification plan by developing C/C++ test cases Develop System Verilog/UVM test bench components and by integrating3rd party VIP components. Simulate and debug at RTL, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure. For a more senior role, you will also Lead a team technically through exploring new environment and identifying potential enhancement areas through new methodology. Identify and setting mid/long term goals based on benchmarking against industry standards. Your Profile You are best equipped for this task if you have: Masters/Bachelors in Electrical Engineering or Computer Science with5-12 years of relevant work experience. Strong foundational knowledge of digital design & verification. Advanced knowledge and hands-on experience of System Verilog and UVM. Hands-on experience in hardware-software debugging at the system or application level. Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills is a plus Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes Dynamic and energetic with zero verification escape mindset Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners. Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives. Knowledge on ISO26262 and ISO21434 are advantageous. Verification experience in COM, CPU peripherals, BUS protocols or pattern development is a plus. Experience in test bench/verification environment set up is also a plus. Candidate who has more relevant working experience will be considered for a more senior position. Contact: Jyoti.Vimal@Infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer - Partial Ability to drive MSV project independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

The role will own verification of one or more IP blocks at IP-level andleading to chip-level for USB and automotive applications. In your new role you will: The role will o wn verification of one or more IP blocks at IP-level andleading to chip-level for USB and automotive applications. The role will be responsible for Testbench Architecture, Test planning,Test Development and Verification for IP Blocks and Subsystems. The role will work on verification closure , including test plan,coverage and assertion closure. The role will Interact with other functional leads from Design, FW/SW,Validation Teams. The role will evaluate new tools & methodologies required forcontinuous improvement of design flows. Guide & Mentor junior engineers working on IP Blocks, Subsystem. You are best equipped for this task if you have: Bachelors/Masters in Electrical/Electronics Engineering with 8+ yearsof experience in Advanced user of System Verilog & UVM for IP , Subsystem, SOC levelverification Exposed to Coverage Driven & Constraint random Verification Experience with Assertion based & Formal Verification Experience with low power design aspects , Power Aware Verification(UPF) and Gate level Experience in verification of designs in RTL & GLS Experience in developing verification architecture Experience in leading a team, create & execute test plan, Coverageclosure Contact: Jyoti.Vimal@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS Job Description In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for S oC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating problem solving mindset Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches Your Profile You are best equipped for this task if you have: Bachelors with 5+ years of experience Mentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture. Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

"> About Us ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start-ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge-building environment. Roles and Responsibility 6-12 Years of experience in DV 6+ years of experience in AMS Verification is a must Responsibilities Experience in Co-simulation (RTL + Spice) Good understanding on Analog blocks Experience in System Verilog, UVM is must Experience in WREAL, RNM, Vams modelling is a plus Desired Skills Experience in WREAL, RNM, Vams modelling is a plus

Need 5 to 10 years of relevant work experience - Requires hands-on experience in developing and understanding building block schematics, memory schematics, and running circuit simulation with spice simulators - Experience in deciphering circuit behavior from schematics - Ability to develop and maintain test benches and test vectors using simulation tools - Familiarity with circuit characterization, timing libraries, timing arcs - Experience in Verilog MOS switch level models and netlist simulation - Knowledge in static timing analysis - Experience in Gate level simulations with SDF back annotation - Ability to debug SDF annotation issues and ensure good coverage - Experience with latch based designs and their timing requirements - Capacity to debug gate level simulation failures and root cause the failures in actual circuits - Hands-on knowledge of System Verilog Assertions to specify expected design behavior - Familiarity with UVM is a plus - Strong communication skills required - Skill in gate level simulation, spice correlation, debugging failures and providing fixes at gate or transistor level - Experience in IP and SoC Verification, particularly with memory or full chip Verification - Proficiency in System Verilog, UVM (Universal Verification Methodology) - Experience in Verification Environment: Testbench Development, debugging and closure of functional coverage - Ability in Gate Level Simulations and Debugging - Knowledge in Python and automation - Familiarity with Static timing analysis (STA) is a plus.

Working with a design team to develop advanced DRAM and Emerging memory products using state-of-the-art memory technologies. - Verifying high-density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high-speed designs, and complex functionality. - Evaluating block level functionality/fullchip level and providing solutions for functionally correct design. - Collaborating with various design and verification teams across the globe. - Providing verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing and maintaining test benches and test vectors using simulation tools and running regressions for coverage analysis and improvements. - Participating in the development of new verification flows for challenges in DRAM and emerging memory design. - Developing verification methodology and verification environments for advanced DRAM and emerging memory products. - Understanding and using digital/mixed signal circuits and verification tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice. - Writing Verilog and Real Number Models. - Building SV testbenches at Block and Fullchip Level. - Using SV, UVM based Verification and scripting using Perl and Python. - Previous work experience in DRAM memory related fields is preferred. - Good communication, debugging skills and ability to work well in a team are required. - Understanding the usage of tools like Cadence (Xcellium, Simvision), Synopsys (VCS, Verdi), and Mentor (Questasim) simulators.

As CPU/Processor Nest Verification Lead, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation IBM Power Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Electronics / Micro Electronics / Computer Science with strong programming skills is required. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise As a CPU/Processor Nest Verification lead, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, Fabric, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems and providing technical guidance to junior/mid-level engineers in the team. Key Duties: Verification Environment Ownership:Take charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and Communication:Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered.Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in IBM Server Processors. Technical leadership :Providing Technical leadership to the senior/mid-level engineers who will be working closely with you. Stakeholder management :Managing and influencing stakeholders technically, periodic update in status meeting/technical forums. Functional Verification Experience: 15+ years of extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies and technically leading a large team. Computer Architecture Knowledge: Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains. Multi-processor Cache Coherency Transport Fabric :Experience in functional verification of system level Coherency Transport Network designs and ways to stress verify them. Strong programming skills :Proficiency in C++, Python scripting or similar languages. Preferred technical and professional experience Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design. Experience in specifying and developing the verification infrastructure for verifying processor based designs. Minimum one full life cycle experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect/Fabric Verification. Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects

Creates quality Pre-Silicon Validation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/ FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to Pre-Silicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Job Experience: Technical experience in verification of RTL-based digital systems with very good understating of various system level flows. Experience leading development of verification architecture based on evolving requirement from IP/SOC customers. Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/ SystemC based verification techniques. Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments. Experience in SW Programming/scripting and debug such as C, C++, Perl, Python. Work experience creating a self-checking emulation/simulation test bench. Highly proficient in UVM techniques for verification. Hands-on experience of emulation and simulation BFM based verification. Good understanding of architectural design documents(micro-architecture documents, integration documents). Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence ). Protocol knowledge : PCIE, CXL, UCIe, CHI, DDR Good understanding of CPU architecture (Intel/AMD/ Arm/GPU). Highly proficient with coherent, non-coherent and concurrent traffic validation. Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce Experience in building emulation based models for large scale designs is a plus. Job Responsibilities: Work closely with peers in architecture, design and verification teams Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP's. Maintain generic emulation-based verification environment and regression setups for various IP'sLeads activities driving the development of various stimulus to support the emulation based verification of various IP's. Develop and maintain UVM environments for IP interfacesWork in cross-functional teams to deliver bug free features in a timely manner Qualifications This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus. Minimum Qualifications: Must have a Bachelor's degree with 10+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 7+ years.

Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 3 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 5 years of relevant industry experience. Experience: Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification. Experience in verification of design blocks (IP) for system-on-chip (SoC) components. Experience in system verilog, and/ OVM or UVM based verification methodologies. Experience in one/more of the following areas PCI_Express, USB, I3C, MIPI and /or AMBA standards (OCP, AXI, AHB etc.). Knowledge of scripting, SVA. Knowledge of IO Interconnect is a plus. Knowledge of considerations for performance, power and cost optimization is desirable. Expected to be thorough with general verification concepts with System Verilog/ OVM/UVM- Writing test cases and making scoreboard/infrastructure changes to the environment. Ownership/ coding/enhancement of functional scoreboards/ agents/sequences/ monitors. Knowledge in FPV is good to have. Responsible for understanding architecture spec and deriving test cases / test plans. Need to be a key team player, while being highly energetic and motivated, independent and self-driven (with minimal mentoring/ handholding)- Expected to define functional coverage/ code/hit it through sequence enhancement and newer/directed test.

Job Description In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques Implementing f unctional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes. Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 7+ years experience in constrained-random, coverage driven verification environments. Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations. Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in ord

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Candidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads. Necessary skills/experience:"¢ 3+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory) "¢ 2+ years of experience in technical leadership role with or without direct reports "¢ Experience in power aware simulation is a big plus "¢ Experience on camera verification is a big plus "¢ Expertise in Coverage closure , RTL debug skills "¢ Expertize in SV "“ UVM, Assertions based verification, DPI "¢ Familiarity in Firmware/emulation (ex:Veloce) based verification , GLS "¢ Familiarity with bus protocols like AHB, AXI, ARM based system architecture "¢ Experience with Perl, Python, or similar scripting language "¢ Excellent problem solving skills & Verification aptitude Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologies:JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation Get to work on the latest and cutting-edge tech nodes Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure. Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . Candidates should have 5-8 years experience. Good in SV, UVM, Assertions, GLS Solid knowledge of C and Scipting language like python Working knowledge of bus protocol like AHB/AXI Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools "“ working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 3 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education Requirements BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools "“ both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role : Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks :gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of experience in Design Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.