Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 3-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skillset/Experience: 3-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team. Create DV infrastructure for verification. Integrate VIP's Create and execute test plans, debug failures, write assertions, close code and functional coverage. Ensure high quality verification. Working with all stakeholders to ensure program success. Minimum Qualifications Bachelors degree in engineering, Electronics, Information Systems, Computer Science, or related field. 5+ years Hardware Engineering experience or related work experience. Preferred Qualifications Following skill set is required: Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved. Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 7+ Year of industry experiences in the following areas:- Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Good understanding of System memory management unit, NOC is a plus. Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization. Good communication and positive attitude towards work. Ability to maximize the productivity with great collaboration and teamwork Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are hiring across mutliple roles in the below domain: 1. Physical Design 2.RTL Design 3. Design Verification 4. STA/ Synthesis 5. DFT 6. FPGA Emulation 7. Validation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Software Engineer II Location: Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing learning opportunities, and celebrating success in recognition of the specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirements and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary As a software engineer II, you will work on the latest specs to develop, optimize and enhance the VIP codebase for performance, scalability, and reliability, ensuring adherence to industry standards and best practices. You will also collaborate and work closely with architects, verification engineers, and other R&D teams to understand requirements and contribute to the overall development roadmap. In this role, you will be an integral part of developing advanced Verification IP solutions, contributing to the innovation and reliability of our products. This involves working closely with the customers to understand their key challenges, develop efficient methodologies, help them leverage the latest tool capabilities, and guide them to achieve their design goals. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and influence at all internal and external levels. You will be participating actively in brainstorming sessions, contribute creative ideas, and explore new technologies to improve and expand our VIP offerings. Experience and Technical Skills required 2 to 5 years of experience in verification Expertise in SV, UVM, Verilog Good understanding of functional coverage and Randomization Good understanding of C/C++ languages Knowledge of scripting languages & VIP development is a big plus Must have excellent debugging skills and the ability to separate out the critical issues from trivial ones. Job Responsibilities : Quickly ramp up on new technologies Independently develop the new functionalities/features in C/C++ Develop and execute a verification plan Test plan and test bench development in SV/UVM Functional Coverage creation Debugging complex issues independently Committed to delivering high-quality features in the defined timeline Qualifications: BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Position Description: Design Verification role for IP development team. B. Tech/M. Tech with 10+ years of relevant experience. Position is based in Bangalore/Noida, part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs. In addition to UVM functional verification, role could involve Formal verification of complex design modules. In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs. Understand design and produce detailed verification strategy and test plan. Self-starter and learner with passion for getting the job done on time with great quality. Strong problem solving, analytical and debug skills Excellent verbal and written communications skills Clearly communicate project status, issues etc. Behavioral skills required: Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Ability to establish a close working relationship with both customer peers and management. Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities Design Verification for interconnect IP Relevant experience in interconnect and subsystems is strongly preferred Crafting verification plans and executing on those plans to verify highly complex and configurable designs. Responsible for coverage collection and closure Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope Required Skills and Experience: 8+ years of design verification experience BS (or higher) in EE/Computer Engineering Strong technical and interpersonal skills Excellent knowledge of Interconnects, NoCs and design verification fundamentals. Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches Experience with development of fully automated flows Exposure to scripting languages like Perl, Unix shell or similar languages Experience with Formal Verification will be a plus Experience with Gate Level Simulations Excellent written and oral communication skills necessary We re doing work that matters. Help us solve what others can t.

Develops pre Silicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. In this highly visible and interactive role your primary responsibilities will include: Understanding given Graphics(Media, Display, Image Processing Unit), AI (Neural Processing Unit), DFD (design for debug), D2D/Ucie cross-die interface and SoC Power Management clusters u-architecture understanding, SoC/SS Integration or IP test plan development, SOC/Subsystem/IPs Test-Bench infra. Definition/development, Val content (test/sequence/cov/assertions) development and signing off all define Verification milestones for Regression/coverage side. Qualifications BE or B Tech or M Tech ECE or Computer Science with 5-10 years SoC ,Subsystem ,IP verification experience. Minimum 5 to 10 year of relevant experience in SoC/Sub-system/IP integration and verification ie developing IP verification components, integrating IP verification content to SOC/SS preparing and executing test plan for complex clusters, subsystems. Good understanding and working experience in System Verilog/UVM, Verilog and scripts perl shell Knowledge and hands on experience in Industry Standard Verification Methodologies eg UVM. Hands on experience in Industry standard simulation and debugging tools ie VCS and Verdi etc. Working experience and good understanding of state of art verification technologies i.e .coverage and assertion based formal verification and HW assisted verification. Good understanding of Graphics(Media,Display,IPU), AI [NPU], DFD (design for debug), D2D/Ucie and Power Management clusters. Excellent debugging and analytical abilities. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Good understanding of analog / mixed signal circuits. Experience in Analog and Mixed signal Verification, understand the usage of tools like Virtuoso, Finesim, Hspice, Xcellium, Simvision, Waveview. Hands on experience in writing Verilog Models. Verilog A/MS, RVM model writing is a plus. Hands on experience in building SPICE testbenches at Block, Full chip Level. Hand on experience in building the COSIM/ Mixed signal verification environment is a plus. Hands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using Perl, Python is a plus. Previous work experience in memory related fields is a plus. Must possess good communication, debugging skills and ability to work well in a team.

JD: Verification Engineer 8 years experience Job Overview Duties include As a Verification engineer, should have the hands-on experience related to block level, sub-system level and chip top level verification. Development and working with object-oriented verification languages (System Verilog, UVM) Have background in Mixed Signal devices. Able to handle multiple blocks (good at time management). Good at debugging design and environment related issues. Should work closely with the designers to understand the design changes and implement the same in Verification. Should be good with scripting languages. Essential Functions Should be good at Digital basics. Develop environment and tests for block level verification and extend the same to block and chip top level verification. Good understanding of RAL, Code coverage and functional coverage and implementing the same Scripting using Perl, Python and Shell Simulations using gate level netlist at various PVT corners. Generation of vcd files for power analysis. Ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced work environment. Process : If the resume is shortlisted, the candidate should come to the Aura office for the F2F discussion ( 3 rounds of discussion on the same day) If shortlisted he should be ready to start immediately We are in 5 days WFO mode & no Hybrid mode

Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and System Verilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

About Marvell . Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system level knowledge, Marvells infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Lead DV efforts for blocks, subsystems, and top-level verification. Develop and maintain UVM-based verification environments. Define and review test plans with architecture and design teams. Verify designs using directed and constrained random techniques. Maintain regression, debug failures, and analyze coverage. Drive verification to meet coverage targets. Contribute to next-gen data processing and hardware accelerator verification. Focus on networking domain verification for future solutions. Ensure design closure using innovative and automated techniques. What Were Looking For Bachelor s or Master s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Strong experience with Verilog, SystemVerilog, and UVM. Expertise in unit and subsystem verification, modern verification concepts. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred). Strong debugging skills and verification flow optimization. Collaborate with design teams on specs, test plans, and verification strategies. Develop and maintain UVM-based testbenches for ASIC SoCs. Execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Qualifications:BE , MTech in EC/EE. 4+ years' experience. Expertise in PCIe , Ethernet domain is a plusMinimum Qualifications:Bachelor's in Electronics Engineering with at least 4 yrs of experience in the following areas (master's degree may offset experience partially).Documentation related to bachelor's degree completion will be required.Frontend Development and related areas.Knowledge in RTL IP design , previous experience in RTL designExpertise in System Verilog, RTL coding.Digital Design Techniques.Possesses strong analytical and debug skills.Intermediate to advanced English level.Motivated for innovations in domain knowledge Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 5+ years of industry experience, or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 3+ years of industry experience Years of experience must include at least three of the following skills: Hardware architectures, system level IC design implementation knowledge of how to create end use scenarios IP level or SoC level validation experience Processor-based SoC level verification, in native Verilog, SystemVerilog and UVM mixed environments Verification tools such as VCS, waveform analyzer and/or third-party VIP/BFM integration (e.g. Synopsys VIPs) UVM verification Strong understanding of design concepts and ASIC flow Preferred Qualifications and experience that will make you stand out: Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable Understanding of AXI-AMBA. Protocol variants is desirable Strong technical background in FPGA prototype emulation and debug Proven technical background in silicon validation, failure analysis and debug Validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART Prior hands-on automation script development and optimization using C/C++, Python Good understanding of embedded firmware/software development process Functional knowledge and experience in JTAG Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in electrical engineering or computer engineering with 4 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 3+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Monitoring and improve existing simulation environments and simulation efficiency. Experience with Debugging and ACM domain will be a plus. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 3+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Power Management and memory domain will be a plus. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job Description The Memory IP Group (MIP) within the Client Computing Group (CCG) is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products. In this role you will perform all aspects of the functional verification flow to ensure design will meet specification requirements. You will perform IP Verification related tasks such as creating test plan, defining TB architecture and creating test benches, validating design and micro-architectural implementation. You will be automating validation tasks to drive efficiency. You will be analyzing results and help to debug issues in pre-silicon environment at IP, subsystem and SOC level. You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. The additional responsibilities include: development of validation strategies and plans, scoping and driving execution for different area of pre-Si validation, driving technical reviews of plans and proofs with design and architecture teams, maintaining and improving existing functional verification infrastructure and methodology, providing guidance and help to team members in understanding issues, removing roadblocks and ensuring issue resolution through strong demonstration of Intel Cultural values. Qualifications Candidate must possess a BS, MS degree with 10-15 years of relevant industry experience in Design verification, System Verilog and OVM/UVM. Candidate must be experienced in validation flow right from test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS Capable of multitasking in dynamic environment with multiple teams from different geos Solid verbal and written communication skills Excellent debug and problem solving skills Preferred Qualifications: Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols Good scripting skills in Python/Perl Exposed to Formal Property Verification and Git/Perforce/CVS version control

Role & responsibilities Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Preferred candidate profile Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 5+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for Ethernet or PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB , I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Excited to shape the future with cutting-edge AI flagship products? Join our dynamic team! Please share your updated resume and take the next step in your career. Thanks & Regards

ASIC Verification Engineer ODC Project (Automotive Chip) | ACL Digital Location: Pune, Bangalore, Chennai Notice Period: Immediate to 30 Days ACL Digital is hiring ASIC Verification Engineers for a long-term (4+ years) Offshore Development Center (ODC) project in the Automotive domain. We are looking for experienced professionals with expertise in UVM-based verification and high-speed serial protocols. Job Responsibilities: Perform IP, Subsystem, and SoC-level verification Develop UVM testbenches, test plans, and coverage analysis Work on high-speed serial protocols including PCIe, UCIe, SerDes, Ethernet, DDR, LPDDR, SATA, USB, MIPI Debug and resolve complex verification issues Collaborate with cross-functional teams for design and verification closure Key Requirements: Experience Level: 6 – 20+ Years (Senior Engineer to Sr. Lead) Hands-on experience in UVM-based Verification Strong Debugging & Problem-Solving Skills Experience with industry-standard EDA tools such as Synopsys, Cadence, and Mentor Graphics Why Join Us? Work on an Automotive Chip ODC Project with a 4+ years commitment Collaborate with top industry experts Opportunity for growth and exposure to cutting-edge technologies Interested candidates can share their resumes at prabhu.p@acldigital.com

5+ exp in verification at IP/sub-system level. Well versed in (Digital design, SV, UVM). Experience in DDR, PHY protocols. Responsibilities: Develop and execute comprehensive verification plans and testbenches. Write high-quality, efficient, and reusable verification components. Create and maintain detailed verification documentation. Debug complex verification issues and propose solutions. Collaborate with design engineers to ensure design quality and performance. Stay up-to-date with the latest verification methodologies and tools.

Dear Applicants We, Cyient is hiring for Technical Specialist: Analog Mixed Signal Verification for End to End Offshore-Onshore Model based Global Product R&D from scratch-based Opportunity. Base Location: Bangalore, Pune & Hyderabad Experience Range: 2-12 Yrs Key Skills: Have at least 2yrs experience in AMS verification Have sound knowledge of AMS verification flow Have sound knowledge of different modeling techniques (WREAL/electrical/SV RNM) Have experience in PMIC blocks (like Buck, Boost and LDO) AMS verification Have basic understanding of SV UVM Be good in basic Analog, Digital and AMS concepts Be good in oral and written communication Interested AMS Verification Specialists, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion. Thanks and Regards Rajani Kant Sharma Sr Recruiter: Global Lateral Hiring: Semicon Vertical Cyient

The candidate will also have to mentor junior engineers Experience: 5 to 8 Years of experience in the following areas: Functional Modeling & Verification: Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Languages Expertise C, C++, Python, System C, SystemVerilog/UVM will be a plus Tool Expertise VisualStudio, Git, Bitbucket Education & Soft skills: Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background Strong Problem Solving Efficient Communication Team Leading & Mentoring skills Job responsibilities: Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups etc

Exciting Opportunity for Senior Design Verification Engineer at Scaledge Are you seeking a challenging and rewarding opportunity in the semiconductor industry? Look no further! Scaledge is on the hunt for a talented Senior Design Verification Engineer to join our elite SoC team in Bengaluru/Hyderabad/Bhubaneswar/Pune/Ahmedabad. If you have 5+ years of experience in design verification and a passion for cutting-edge technology, this could be the perfect fit for you! About the Role: As a Senior Design Verification Engineer at Scaledge, you will play a crucial role in ensuring the quality and reliability of our advanced System on Chip (SoC) designs. You will collaborate closely with various teams, crafting comprehensive verification strategies, developing test environments, and driving continuous improvement in verification methodologies. Key Responsibilities: Develop Verification Strategies: Design and implement detailed verification plans for complex SoC designs. Create Test Environments: Build and maintain robust test environments and test benches using industry-leading tools. Verify SoC Components: Conduct block and system-level verification using simulation and formal verification techniques. Debug and Resolve Issues: Identify and fix design and verification issues efficiently. Collaborate Across Teams: Work with design, architecture, and software teams for seamless integration and verification. Enhance Processes: Drive continuous improvement in verification processes and methodologies. Qualifications: Educational Background: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5+ years of hands-on experience in design verification, particularly with SoC. Technical Skills: Proficiency in HDL (Verilog, VHDL) and verification tools (UVM, SystemVerilog). Problem-Solving: Strong analytical and problem-solving skills. Communication: Excellent communication and collaboration skills. Why Join Scaledge? Innovation: Work on groundbreaking technology in the semiconductor industry. Collaborative Environment: Thrive in a team-oriented, innovative workplace. Career Growth: Access opportunities for professional development and career advancement. Competitive Compensation: Enjoy a competitive salary and benefits package. If you are ready to elevate your career and be part of a collaborative and innovative work environment, apply now! Send your updated resume to careers@scaledge.io with "Senior Design Verification Engineer" in the subject line. Join us at Scaledge and be part of our exciting journey in the world of semiconductor innovation!

Exciting Opportunity for Senior Design Verification Engineer at Scaledge Are you seeking a challenging and rewarding opportunity in the semiconductor industry? Look no further! Scaledge is on the hunt for a talented Senior Design Verification Engineer to join our elite SoC team in Bengaluru/Hyderabad/Bhubaneswar/Pune/Ahmedabad. If you have 5+ years of experience in design verification and a passion for cutting-edge technology, this could be the perfect fit for you! About the Role: As a Senior Design Verification Engineer at Scaledge, you will play a crucial role in ensuring the quality and reliability of our advanced System on Chip (SoC) designs. You will collaborate closely with various teams, crafting comprehensive verification strategies, developing test environments, and driving continuous improvement in verification methodologies. Key Responsibilities: Develop Verification Strategies: Design and implement detailed verification plans for complex SoC designs. Create Test Environments: Build and maintain robust test environments and test benches using industry-leading tools. Verify SoC Components: Conduct block and system-level verification using simulation and formal verification techniques. Debug and Resolve Issues: Identify and fix design and verification issues efficiently. Collaborate Across Teams: Work with design, architecture, and software teams for seamless integration and verification. Enhance Processes: Drive continuous improvement in verification processes and methodologies. Qualifications: Educational Background: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5+ years of hands-on experience in design verification, particularly with SoC. Technical Skills: Proficiency in HDL (Verilog, VHDL) and verification tools (UVM, SystemVerilog). Problem-Solving: Strong analytical and problem-solving skills. Communication: Excellent communication and collaboration skills. Why Join Scaledge? Innovation: Work on groundbreaking technology in the semiconductor industry. Collaborative Environment: Thrive in a team-oriented, innovative workplace. Career Growth: Access opportunities for professional development and career advancement. Competitive Compensation: Enjoy a competitive salary and benefits package. If you are ready to elevate your career and be part of a collaborative and innovative work environment, apply now! Send your updated resume to careers@scaledge.io with "Senior Design Verification Engineer" in the subject line. Join us at Scaledge and be part of our exciting journey in the world of semiconductor innovation!