Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview Qualcomm WLAN HW team in Bangalore is responsible for developing and delivering best in class WLAN/WiFi solutions which are setting benchmark in wireless industry. In this role of WLAN Verification Engineer, you will be verifying the PHY Sub-System from both TX and RX perspective. The responsibilities will majorly include : Understanding of WLAN PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems Develop test plan to verify WiFi Standards including 11BE, sequences and design components. Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches Successful candidate will be required to collaborate with worldwide design, silicon, and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills . 3+ years industry experience with below skillset : Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Good understanding of WiFi Standards is a plus Experience with GLS, and scripting languages such as Perl, Python is a plus Education Requirements BE/BTech/ME/MTech/MS Communication Engineering and/or Electronics, VLSI from reputed university preferably with distinction Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

About The Role : You will be part of world class Intel Emulation Solutions team (ES) team responsible for driving the Emulation strategy across Intel's next generation products. ES team is leading the innovations and new technologies with Virtual Platform/Emulation/Hybrid solutions partnering with Intel teams as well external EDA vendors accelerating Intel product TTM. In this role you will be responsible for defining and developing new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation model usability for preSilicon and postSilicon functional validation as well as SW development/validation. You will also develop improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. You will interface with and provide guidance to preSilicon Validation teams for optimizing preSilicon validation environments, test suites and methodologies for emulation efficiency. You will be responsible for developing and applying automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Qualifications Must have a Bachelor's degree or Master's degree in Electrical, Electronics or Computer Engineering with relevant experience of at least 3+ years Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large scale designs Strong understanding of Computer architecture, design principles, validation methodologies and tools Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques. Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments. Experience in SW Programming/scripting and debug such as assembly, C, C++, Perl, Python Prior expertise in CPU, Coherency, reset, Global Flows, Power management, memory, PCIe highly desirable Prior experience in System Validation is a plus. Must possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Performs functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements. Defines and develops scalable and reusable IP verification plans, test benches, and architecture for verification environment to ensure coverage to confirm to graphics microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with GPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Minimum Qualifications: BE/Btech in Electronics or Computer Engineering or any STEM related degree with 6+ year of relevant experience in front end verification at unit/block/IP level or Master's Degree in Electronics or Computer Engineering or any STEM related degree with 5+ years of relevant experience in front end verification at unit/block/IP level Test Bench bring-up at unit/block/IP level and strong programming skills in System Verilog, OVM or UVM. Basic knowledge/Experience on End to End Val cycle, starting from Test Plan till coverage closures/val sign-off. Must be able to work individually with minimal dependency/inputs and should be able to help juniors. Experience with industry standard frontend design and verification flows, tools, methodology Preferred Qualifications: GPU Verification will be a plus Prefer understanding of Graphics architecture. Expertise with RTL verification and validation microarchitecture using Verilog, System Verilog Experience with coverage driven verification testbench development functional modelling and test writing. Experience with scripting shell, PERL, any other language. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Looking for 4+ yrs of design verification Engineers with below skills Developed verification methodology and test plan for new design Good knowledge on the verification flows, SV and UVM Perform RTL code coverage and functional coverage, formal analysis Be responsible for defining the verification strategy and plan for the development Develop coverage-driven verification test plans Knowledge on assertion development and coverage improvement Write test specifications (plans) and create directed and random test cases Good debugging skill

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. We are seeking an experienced ASIC Verification Manager/Lead to lead the verification efforts for ARM multi core advanced CPUs based designs. The ideal candidate will have a strong background in RTL verification methodologies, UVM, C and SystemVerilog, along with proven leadership skills in managing and technically guiding verification teams. You will be responsible for driving pre-silicon verification, collaborating with cross-functional teams, and ensuring the successful validation of high-performance SoCs. Why Join Us Opportunity to work on cutting-edge ARM-based SoC designs. Lead a team in a high-impact, fast-paced environment. Competitive compensation and career growth opportunities. Work alongside some of the best minds in the semiconductor industry. What Youll Do Lead and manage the ASIC verification team to ensure high-quality verification of ARM Advance CPU based SoC designs. Define and implement verification strategies, test plans, and methodologies, release flows for complex IP and SoC design. Develop and maintain UVM-based and C-based testbenches, including constrained random testing, functional coverage, and assertions. Drive pre-silicon verification and support emulation, and FPGA prototyping. Collaborate closely with design, architecture, software, and post-silicon validation teams to ensure comprehensive verification coverage. Analyze and debug simulation failures, regressions, and coverage gaps to ensure complete verification closure. Drive automated verification infrastructure to improve efficiency and reliability. Mentor and guide junior engineers, fostering a culture of innovation and technical excellence. Track project milestones, verification progress, and report status to stakeholders. What Youll Need Bachelor s/Master s degree in Electrical Engineering, Computer Engineering, or a related field. 15+ years of experience in ASIC/SoC verification, with at least 3+ years in a managerial and leadership role. Expertise in ARM architecture, AMBA protocols (AXI, AHB, APB), and memory subsystems, PCIe, D2D Technologies. Strong hands-on experience with UVM, SystemVerilog, and functional verification methodologies. Experience with Excelium, VCS, Questa, or other industry-standard simulators. Familiarity with Formal Verification, Gate level Simulations, Static Timing Analysis, and UPF based Power-aware Verification. Hands-on experience in C/C++, Python, or Perl scripting for automation. Experience with Emulation, FPGA prototyping, and hardware-software co-verification is a plus. Excellent leadership, communication, and problem-solving skills. Preferred Qualifications: Experience in high-performance computing (HPC) or data center SoC verification. Knowledge of Arm architecture, Security verification, and Cache coherency protocols. Familiarity with post-silicon validation and bring-up processes. Prior experience working in tapeout-focused environments. We have a flexible work environment to support and help employees thrive in personal and professional capacities. As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

3-6 years of experience in AMS Verification Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.)

As a Principal Memory Circuit Design Verification Engineer you will work in a highly innovative, motivated, Upbeat, and dynamic design team capable of verifying complete products using innovative memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally accurate design. Unique Opportunities Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as HBM,DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work with international colleagues on developing new verification flows to take on the challenges in design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Core Requirements Good communication skills and ability to work well in a team Guide new team members and energetic engineers in the team Analytical capability for complex CMOS and/or gate level circuit designs Proficient with either SPICE and/or Verilog simulations Qualifications & Skills Experience in SystemVerilog, PLI coding, Gate Level Sims Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience 4 years of experience with verification methodology such as Universal verification methodology (UVM) 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc Experience with SystemVerilog, SVA, and functional coverage Preferred qualifications: Master's degree in Electrical Engineering or a related field Experience with industry-standard simulators, revision control systems, and regression systems Experience with the full verification life cycle Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units Excellent problem solving and communication skills About The Job In this role, youll work to shape the future of AI/ML hardware acceleration You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications Youll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems In this role, you will own the full verification life cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware You will collaborate closely with design and verification engineers in active projects and perform verification Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them We keep our networks up and running, ensuring our users have the best and fastest experience possible Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios Identify and write all types of coverage measures for stimulus and corner-cases Debug tests with design engineers to deliver functionally correct design blocks Measure to identify verification holes and to show progress towards tape-out Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM) Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Minimum qualifications: Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience 5 years of experience in driving/leading functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs) Experience working with System Verilog and Universal Verification Methodology (UVM) Preferred qualifications: Master's degree in Computer Science or Electrical Engineering or equivalent practical experience Experience leading design verification of an SoC or large ASICs Experience in different verification techniques and methodologies, including formal, Gate Level Simulation, Unified Power Format based Power simulations, UVM, etc to achieve bug-free Silicon in complex SoC Experience in scripting languages (e g , Python, Perl) for automation and analysis Experience in driving cross-functional teams for high quality tape-outs About The Job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Be the primary point of contact for IP and SoC functional verification for cross-functional teams Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs Develop high-performance and low power hardware to enable Googles continuous innovations in consumer hardware Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description As Technical Lead – Design Verification, you will be the key contributor of ORAN SoC product design verification team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 10+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space. Key Responsibilities Develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off. Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing. Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, , PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc). Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus. Track record of successfully executing block or chip-level verification plans. Excellent communication and presentation skills, energetic and self-motivated. Work effectively with an off-site/ offshore design and verification teams across locations. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

As a AMS Verification Engineer one should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Job Description In your new role you will: Ability to lead MSV and/or DV verifications. Involved in verification for IPs . Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer. Test plan preparation as per the dynamics of product specifications. Behavioral modeling: Verilog, real or SV-RNM . Dealing challenges with AMS methodologies of Cadence : irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS. Testcase Debug & proposing new scenarios. Ability to strategize optimization of simulation bench for simulation time. Your Profile You are best equipped for this task if you have: Bachelors with 9+ years or Masters with 8+ years of experience. Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage. HDL/HVL : Verilog / Verilog-ams , SV/UVM added advantage. Tools: Cadence Xcelium spectre / Synopsys XA-VCS / Mentor Eldo ADMS . Automation: Perl/python/shell. Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements. Ability to drive projects and debug independently.

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineon's design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the "Universal Verification Methodology" (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management.

Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. KEY RESPONSIBILITIES: Verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate-level simulation, power-aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs . ACADEMIC CREDENTIALS: Require BS w/ 6+ yrs or MS w/ 4+ yrs or PhD w/ 2+ yrs in Electrical Engineering, Computer Engineering or Computer Science.

Execute SoC verification tasks and work closely with team members toreview and understand the relevant functional and safety relatedrequirements. Work and align with different stakeholders to identify verificationplans and define SOC verification strategies Execute the verification plan by developing C/C++ testcases andSystem Verilog/UVM Test Bench components and by integrating 3rd partyVIP components. Your Profile Masters/Bachelors in Electrical/Electronic Engineering with 5-10 years of relevant work experience. oUnderstand the usage of tools like Xcelium, Spectre(X) and Simvision. Strong foundational knowledge of digital/mixed-signal design &verification. Knowledge and hands-on experience of System Verilog and UVM. Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes Self-motivated, flexible and with strong interpersonal skills Good communication with interpersonal skills and is a good teamplayer who is able to work well with both internal and externalpartners. Hands-on experience in hardware-software debugging at the system orapplication level. Hand-on experience with gate-level-simulations and withdebugging/troubleshooting skills is a plus Understanding of UPF context of analog/transistor level Basic analog knowledge for debugging purposes. Experience in automotive industry in Functional Safety ISO26262 andCybersecurity ISO21434 are advantageous

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Job Description Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating problem solving mindset Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches You are best equipped for this task if you have: Bachelors with 5+ years of experience Mentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture. Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements

Work and align with different stakeholders to identify verificationplans and define IP verification strategies Write verification plans to meet these requirements after closealignment with other verification teams for proper work split accordingto mutually acceptable verification assignment. Execute IP verification tasks and work closely with team members toreview and understand the relevant functional and safety-relatedrequirements. Execute the verification plan by developing C/C++ test cases andSystem Verilog/UVM test bench components and by integrating 3rd partyVIP components. Simulate and debug at RTL, Unit and Gate Level using appropriatetools and flows including Simulator, Emulator, Portable Stimulus and/orFormal methodologies for functional and code coverage closure. Lead a team technically through exploring new environment andidentifying potential enhancement areas through new methodology. Identify and drive mid/long term goals based on benchmarking againstindustry standards. Your Profile You are best equipped for this task if you have: Masters/Bachelors in Electrical/Electronics Engineering or ComputerScience with 10-12 years of relevant work experience. Strong foundational knowledge of digital design & verification. Advanced knowledge and hands-on experience of System Verilog and UVM. Hands-on experience in hardware-software debugging at the system orapplication level. Hands-on experience with gate-level-simulations anddebugging/troubleshooting skills is a plus Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes (e.g., Jira) Dynamic and energetic with zero verification escape mindset Self-motivated, flexible, good communication and interpersonal skillsalong with being a good team player and ability to work well with bothinternal and external partners. Candidate has proven ability to achieve results in a very dynamic,multi-site environment and be able to coordinate with the rightpriorities and self-initiatives. Experience in automotive industry in Functional Safety (ISO26262) andCybersecurity ISO21434 are a plus. Verification experience in High and Low Speed Communicationinterfaces, CPU peripherals, BUS and pattern development. Experience in test bench/verification environment development isalso a plus

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVerilog, PLI coding, and UVM Test Benches. * Expertise in DRAM, SRAM, or other memory-related fields. * Familiarity with AMS verification and co-simulation is a plus. * Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful. * Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous. Perks and benefits : Flexible Working Hours , Transport facility, Competitive Salary

Role & osition: Sr vefication engg 1 position exp - 7-10 yrs SV & UVM method, verilog simulation, exp in memory (Not theoretical, BUT practical)- really great SRAM DRAM - v good prf - Masters degree, graduate also ok. gate level simulation, AMS skills good to have Cadence, VCS - normal verification Mentor experience required, not team lead TMSC not required preference will be given to SPICE simulation No protocols required– should be a able to write a test plan, test bench Knowledge on Pearl can be alternative to PLI coding responsibilities Preferred candidate profile Perks and benefits

Grounds up verification environment development using SV/ UVM is a must5+ yrs Bangalore/ Pune One of the Serdes of high speed protocols like PCIe or USB 3 or MIPI Testplanning, AMS Setup, Experience in wreal, RNM, Verilog A VCS Primesim AMS and Primesim XA tool lExperience in wreal, RNM, Verilog A, exp in System Verilog and UVM

Design Verification Staff Engineer - (DDR/SMMU/NOC based IPs and Subsystems) General Summary: Job Overview We are looking to hire a strong DV engineer to work on verification of DDR/SMMU/NOC based IPs and Subsystems in the Infra IP team Create DV infrastructure for verification Integrate VIP's Create and execute test plans, debug failures, write assertions, close code and functional coverage Ensure high quality verification Working with all stakeholders to ensure program success Minimum Qualifications Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field. 4+ years Hardware Engineering experience or related work experience. Preferred Qualifications Following skill set is required: Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 4+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Experience range from 4+ years. Hands-on experience Verilog-AMS, System Verilog, and UVM methodologies. Experience with Cadence Spectre or similar AMS simulation tools, Strong understanding of analog circuit design principles (op-amps, transistors, etc.)

Senior Memory Circuit Design Verification Engineer role in an innovative, dynamic design team - Drive the team and overall verification effort to ensure delivery of functionally correct design - Responsible for fastspice(Primesim / Finesim / spectre) based verification - Guide and set direction for verification effort within areas of expertise - Understand circuitry and perform block level circuit simulation and analysis - Provide verification support by simulating, analyzing and debugging pre-silicon full chip designs - Develop Test cases/Stimulus to increase functional coverage for DRAM and emerging memory architectures - Participate in developing verification methodology and environments for DRAM and emerging memory products - Co-work with international colleagues on developing new verification flows - Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements - Circuit simulation experience is desirable - Knowledge of Analysis of Circuits, Timing concepts, DFT, and schematic analysis - Understanding of UVM and DFT Features, exposure to IEEE1500/JTAG - Perform critical timing, data path timing analysis and simulation based reliability analysis - Complete ownership of verification and end to end analysis of complex full chip gate level custom designs of Micron s HBM portfolio - Collaborate closely with design and verification team members globally - Work closely with cross functional groups such as Product Engineering and Design Architecture - Review vendor capability to support product development - Requires 3-5 years of experience.

Job Summary: 1. Work as a Senior Memory Circuit Design Verification Engineer in a dynamic design team. 2. Responsible for verifying complete products using state of the art DRAM memory technologies. 3. Drive the team and the overall verification effort to deliver a functionally correct design. 4. Responsible for fastspice(Primesim / Finesim / spectre) based verification. 5. Guide the verification effort within areas of expertise in any project undertaken. 6. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. 7. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. 8. Develop verification methodology and verification environments for advanced DRAM and emerging memory products. 9. Collaborate with international colleagues on developing new verification flows for DRAM and emerging memory design. 10. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. 11. Have circuit simulation experience, knowledge in analysis of circuits, timing concepts, DFT and schematic analysis. 12. High level understanding of UVM, DFT features and exposure to IEEE1500/JTAG. 13. Responsible for critical timing, data path timing analysis and simulation based reliability analysis (BTI, HC). 14. Complete ownership of verification and end to end analysis of complex full chip gate level custom designs of Micron s HBM portfolio. 15. Collaborate closely with design and verification team members across the globe. 16. Work closely with cross functional groups such as Product Engineering and Design Architecture. 17. May also review vendor capability to support product development. 18. Requires 3-5 years of experience.

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 10+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience The years of experience mentioned above must focus on formal verification Preferred Qualifications: Knowledge of GPU Formal verification experience in at least one of these areas:Arbitration logic, low power design, memory controller, transaction router/bridge. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.