982 Uvm Jobs - Page 20

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Board Design. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Board Design. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Board Design. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Semiconductor Platform Engineering. Experience3-5 Years.

The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development. This role requires expertise in RTL design, verification, synthesis, and architecture development, along with strong leadership and strategic planning skills. Key Responsibilities Technical LeadershipDefine and implement best practices for front-end ASIC design, ensuring efficiency and performance. Architecture & DesignOversee the development of digital circuits, including RTL coding, synthesis, and timing analysis. Verification & ValidationEnsure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks. Cross-Team CollaborationWork closely with back-end design, physical design, and fabrication teams to optimize chip performance. Innovation & R&DStay updated with emerging semiconductor technologies and drive research initiatives. Mentorship & Team DevelopmentGuide and mentor engineers, fostering a culture of learning and technical excellence. Technical Project ManagementOversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications EducationBachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field. Experience15+ years in ASIC front-end design, with a proven track record of successful projects. Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques. Leadership & CommunicationAbility to lead teams, manage projects, and communicate effectively with stakeholders. Problem-SolvingAnalytical mindset with a passion for optimizing digital designs for performance and efficiency. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: Design world class hardware and software Communicate and work with team members across multiple disciplines Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues. Bachelor s degree or higher in EE, CE, or CS 2+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification. Experience developing UVM test bench, writing testplan, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality and performance with strong overall debug skills. Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python or Perl) for automation Excellent verbal and written communication skills BS in Computer Science, Electrical Engineering, or related field. Experience with CPU block level testing Experience debugging system-level issues Strong programming skills in C/C++ and scripting skills in Python and/or Perl Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Mirafra Technologies is looking for experienced Design Verification Engineers to join our dynamic team in Hyderabad/Bangalore If you're passionate about digital design and verification and want to work on cutting-edge SoC projects, this is the opportunity for you! Key Responsibilities: Develop and execute test plans and testbenches using SystemVerilog/UVM Perform functional and code coverage analysis Debug RTL and testbench issues efficiently Collaborate with design and architecture teams to ensure verification completeness Required Skills: Strong coding skills in Verilog Hands-on experience with SystemVerilog and UVM-based verification Experience in SoC/IP level verification Good understanding of design verification methodologies , assertions, and coverage Familiarity with debugging tools , simulation , and scripting (Python/Tcl/Perl) Preferred Skills: Exposure to high-speed protocols (PCIe, USB, Ethernet) Knowledge of formal verification or power-aware verification is a plus Why Join Mirafra? Work with global semiconductor leaders, gain deep technical exposure, and be part of a growing and collaborative team. Apply Now by sending your resume to swarnamanjari@mirafra.com

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for IP/SoC level verification. Develop test benches from scratch, including creating drivers, monitors, and predictors. Utilize System Verilog to write verification code and debug issues. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer reviews to ensure high-quality deliverables. Desired Candidate Profile 4-10 years of experience in SOC/IP Verification with expertise in DV on Cpu, DDR, Ethernet, PCIe protocols. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of GLS (Global Logic Synthesis) concepts.

Skillset: DV | System Verilog | UVM | Protocol Expertise Must-Have Skills: Strong expertise in System Verilog (SV) and UVM Proven experience in Test Bench Development Deep protocol knowledge in at least one of the following: PCIe / UCIe / CXL / NVM AXI / ACE / CHI Ethernet / RoCE / RDMA DDR / LPDDR / HBM Key Responsibilities : Lead and drive verification for block, subsystem, or SoC level designs Strong experience in IP/subsystem/SoC verification using SV/UVM Verification experience with ARM or RISC-V CPU based subsystems Work with C/Assembly for low-level testing Perform Power Aware Simulations using UPF Location : Bangalore | Hyderabad | Cochin | Pune

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs. Develop test benches in System Verilog for verifying complex digital designs. Collaborate with cross-functional teams to identify requirements and develop test plans. Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging. Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills. Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus. Desired Candidate Profile 5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of SystemVerilog programming language and its application in DV testing.

• Develop SoC verification plans focused on IP block interoperability & SOC/ System level. • Develop RAL test plan at SOC/IP level. • Verify SoC using advanced verification methodologies. • HW/SW Co-Verification environment - test-benches, use-cases. Required Candidate profile • 10+ years in DV full-chip Exp. • Strong in UVM & testbench architecture • SV/UVM testbench & assertion Development • Hands-on RAL model development (UVM) • Interface knowledge: AXI, APB, AHB

Design of DC-DC High Frequency Switching Power Supplies using Analog Devices large portfolio of Power Management Integrated Circuits. New DC-DC Monolithic (Integrated Power and Controller) Power Products definition. Validation of the new generation Power Management Integrated Circuits. Full product life-cycle ownership - Definition, Validation and Market Introduction. Mentor junior Product Applications Engineers Responsibilities include: Development of product evaluation kits and system reference design boards Circuit schematic design and PCB layout creation, review, and release Performance optimization and characterization in application circuits Validate new products, creating new test methodologies. Data collection for datasheets and release notes Collate results with design and test engineers. Technical support for key customers and field engineers Simulation of Power Electronics Converters Take ownership of quality and on-time delivery Minimum Requirements: Masters degree in Power Electronics At least 8 years of hands-on experience in developing switching power supplies. Basic understanding of transistor-level analog circuit design Strong written and verbal communication skills

Verification of mixed signal designs and sub-systems using leading edge verification methodologies. Development of directed and constrained random test cases in System Verilog Architect, implement, and/or manage complete metric-driven System Verilog and UVM verification environments as determined by project complexity Define test plans, tests and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage. Continuous interaction with analog and digital teams in enabling top-level chip verification. Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering team. Minimum qualifications BSEE + 7 years or MSEE + 5 years Digital and/or Mixed Signal IC verification experience. Strong written and verbal communication skills. Strong coding, object-oriented programming, and documentation skills. Strong System Verilog fluency in verification domain. System Verilog Assertion for Dynamic and Formal Verification. Experience in developing test benches, testcases using System Verilog and UVM Knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog Knowledge of and capability to execute the entire digital verification process without significant assistance Preferred qualifications Knowledge/verification of custom digital interfaces (I2C, SPI, UART, etc.). Extensive experience with a scripting language (Perl, Python, C, etc.) Experience with Mixed signal verification Mixed-signal simulation (Cadence AMS), interfacing with analog functions Experience with writing Verilog-AMS and Real Number Models for Analog Functions Familiarity with verification on multiphase DC-DC controllers Experience with verification of ARM/RISC-V based sub-systems or SoCs. Experience with verification of voltage interfaces like PMBUS, AVS, SVID, SVI3. Experience with formal verification methodology

We're looking for a highly skilled Senior Digital Verification Engineer with extensive hands-on experience in SystemVerilog (SV) and UVM methodology. In this role, you'll be instrumental in developing robust verification plans, building reusable testbench components, and driving comprehensive coverage closure for complex digital blocks at various levels. Responsibilities: Collaborate with cross-functional teams to meticulously review and refine architecture and design specifications. Develop comprehensive verification plans for complex digital modules at the IP, Subsystem, and SoC levels. Design and implement reusable testbench components , including drivers, monitors, and scoreboards, utilizing SV-UVM methodology. Work closely with design teams to achieve rigorous coverage closure. Coordinate with silicon test and evaluation teams to develop and deliver effective test patterns. Required Qualifications: Extensive hands-on experience (6+ years) in digital verification using SystemVerilog (SV) and UVM methodology . Proven expertise in developing verification plans for complex digital blocks. Proficiency in creating testbench environments at IP and/or Subsystem levels. Experience in constrained random stimulus generation and coverage closure . Competence in Gate-Level Simulation (GLS) setup and debugging. Strong debugging skills and analytical problem-solving capabilities . Familiarity with ARM-AMBA protocols . Advantageous Skills: Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding. Exposure to mixed-signal verification . Exposure to Ethernet interface standards .

Lead, Develop and deploy best-in-class Emulation/FPGA prototyping tools and methodologies across ADI Product Lines Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow Training, deployment, and support of verification methodologies within ADI Position Requirements : Bachelors/master s degree in electrical/Electronics/VLSI with 4-8 years of experience Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred. Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred Expertised in one or more of scripting languages(shell,python,perl) is highly preferred Proficient in SV, UVM, integration of third party VIPS, Accelerated VIPS is required Experience with Vplan/Testplan development and development of verification environment from ground up is good Experience in common communication protocols such as AMBA,I2C, SPI,UART and Ethernet is an added advantage Should be able to communicate technical details very effectively with both customers (product line teams) and peers Good debugging and analytical skills

Lead, Develop and deploy best-in-class Emulation/FPGA prototyping methodologies and execution across ADI Product Lines Proficient in developing unit and SoC level test benches using UVM Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology etc Skilled in enabling emulation for Software development and validation Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow Training, deployment, and support of verification methodologies within ADI Position Requirements : Bachelors/master s degree in electrical/Electronics/VLSI with 8-12 years of experience Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred. Experience in bringing up designs from scratch in Palladium/Protium is highly preferred Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred Expertised in one or more of scripting languages(shell,python,perl) is highly preferred Expertised in SV, UVM, integration of third party VIPS, Accelerated VIPS is required Experience with Vplan/Testplan development and development of verification environment from ground up is required Experience in common communication protocols such as AMBA,I2C, SPI,UART is required and Protocols like JESD, Ethernet is good Should be able to communicate technical details very effectively with both customers (product line teams) and peers Good debugging and analytical skills

Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collaborate with a wide technical community, gaining exposure to diverse technologies and products, all while building a promising career. Job Responsibilities: Formal Verification Planning and Execution: Develop and execute comprehensive formal verification plans for complex digital designs, including both block-level and system-level components. Define precise verification goals, metrics, and coverage targets to ensure exhaustive validation of design functionality. Model Development and Property Writing: Create robust formal models and assertions using industry-standard formal verification tools and techniques. Write and debug properties, constraints, and assumptions to rigorously verify design intent and proactively identify corner-case issues. Debugging and Issue Resolution: Analyze counterexamples and debug failures to pinpoint the root causes of design issues. Work closely with design and RTL teams to efficiently resolve issues and ensure complete alignment with design specifications. Tool and Methodology Expertise: Utilize advanced formal verification tools such as JasperGold, Questa Formal, or equivalent, to perform exhaustive verification. Stay updated on the latest advancements in formal verification methodologies and tools, actively driving their adoption and continuous improvement within the team. Collaboration and Communication: Collaborate effectively with architects, designers, and validation engineers to deeply understand design requirements and constraints. Documentation and Reporting: Document formal verification strategies, methodologies, and results for future reference and auditability. Generate detailed reports summarizing verification coverage, key findings, and actionable recommendations. Position Requirements: Bachelor's or Master's degree in Electrical/Electronics/VLSI with 4-6 years of relevant experience. Demonstrated experience with Formal tools such as Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, with prior implementation experience on SoCs, CPUs, GPUs, or other high-performance computing devices. Proficiency in writing SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Solid understanding of digital design concepts, RTL design, and hardware description languages (Verilog, SystemVerilog, VHDL). Strong analytical and debugging skills to effectively identify and resolve complex design issues. Ability to analyze counterexamples and provide actionable feedback to design teams. Excellent communication and interpersonal skills to work effectively in a collaborative team environment. Familiarity with scripting languages (Perl, Python, TCL) for automation. Experience in common communication protocols such as ARM AMBA, I2C, SPI, UART is preferred.

In your new role you will: Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the Universal Verification Methodology (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs; Your Profile You are best equipped for this task if you have: You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener

We are seeking a results-oriented Senior Digital Verification engineer to join our team focusing on development of the next generation of ADI s Gigabit Multimedia Serial Link products delivering best-in-class solutions for in-car infotainment and advanced driver-assistance systems (ADAS). A small amount of travel is expected. The position offers opportunities for development. JobResponsibilities: Verification of complex ASIC chips and sub-systems using leading edge verification methodologies Define test plans, tests and verification methodology for block and chip level verification. Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, functional/code coverage, formal verification etc to reach verification goals. Take complete ownership for a complex feature verification and technically mentor & guide junior verification engineers. Define and implement improvements in verification flow and methodology. Gate level simulations and debug of large digital blocks and full-chip ASICs Support post-silicon validation activities of the products working with design, applications and test team. Job Requirements: Bachelors or masters degree in Electrical or Computer Engineering with 7+ years of experience in digital verification. Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python. Firm understanding of constrained random functional verification, coverage, and assertions. Expertise in test plan development and development of verification environments from ground up. Extensive experience with verification of complex blocks, regressions and coverage closure. Experience with gate level simulations and debug. Excellent debugging, analytical and problem-solving skills. Strong inter-personal, teamwork and communication skills. Expected to be highly independent, proactive and result-oriented to achieve verification goals. Preferred qualifications: Knowledge of Video (DisplayPort, CSI/DSI), PCIe, Ethernet, I2C, UART, SPI and Audio I2S protocols.. Experience with lab silicon bring-up, validation and production test support. Experience in technically mentoring, coaching junior engineers.