982 Uvm Jobs - Page 17

Description We are seeking a skilled Verification Engineer to join our team in India. The ideal candidate will have a strong background in digital design verification and will be responsible for ensuring the quality and reliability of our products through rigorous testing and analysis. Responsibilities Develop and implement verification plans and test cases for digital designs. Perform functional and performance verification using simulation and formal verification techniques. Collaborate with design engineers to understand specifications and requirements. Debug and analyze issues found during verification, providing feedback to design teams. Generate reports and documentation for verification activities and results. Skills and Qualifications 3-6 years of experience in GLS verification engineering or related field. Strong knowledge of digital design concepts and verification methodologies. Proficiency in SystemVerilog and UVM (Universal Verification Methodology). Experience with simulation tools like ModelSim, Questa, or similar. Familiarity with scripting languages such as Perl, Python, or TCL for automation tasks. Understanding of RTL design and coding practices. Ability to work collaboratively in a team environment and communicate effectively.

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Staff Engineer, DV We are seeking a highly motivated and experienced Staff SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities - MCU-Level UVM Verification: Implement modular UVM testbenches for SoC subsystems (e. g. , sensor hubs, AI accelerators, communication fabrics). - Develop coverage-driven verification plans (functional, code, assertion coverage) aligned with automotive safety and security requirements. - Debug complex SoC-level scenarios (e. g. , multi-protocol interactions, power-aware verification). Automotive VIP Integration: Integrate and customize 3rd-party VIPs (e. g. , Synopsys, Cadence, Mentor) for automotive protocols. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer -GLS Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements: Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus TekWissen Group is an equal opportunity employer supporting workforce diversity.

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Sr Engineer, DV We are seeking a highly motivated and experienced Sr SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities Power-Aware UVM Verification: Execute UPF-driven testbenches to validate power management features: Power gating, isolation, retention. State transitions verification and Verify low-power sequences UPF strategies for hierarchical power domains and Debug power-related failures (e.g., isolation violations, retention flop corruption). Integrate power-aware assertions and coverage metrics. SoC-Level Verification: UVM environments for multi-power-domain SoCs (e.g., processors, interconnects, peripherals). - 4+ years of Experience required. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

CPU Verification Engineer in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: As a CPU Verification Engineer, you will be a key member of the design verification team at Ampere to deliver our high-quality next generation AI integrated, cloud-native server class SoCs. You will be responsible for defining verification strategies and architecting solutions for complex verification problems. You will partner with stakeholders in adjacent domains and enable verification team to left shift bug hunting and meet verification goals on schedule. Youll be involved with all aspects of product development starting with specifications through tape-out and product launch Define strategy and requirements for block level and chip level testing infrastructure Create test plans for unit-level and chip-level verification Design and implement test benches and verification environment Develop random test generators to generate tests and debug failures Code and analyze coverage to meet product quality requirements Define post-si validation plans and debug post-silicon system level failures B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience, or M.Tech with 2+ years of experience. Understanding of high-performance multi-core processor architecture and microarchitecture Knowledge of ARM or x86 memory architecture and assembly language is advantageous 2+ years of IP design verification experience, especially in CPU or Graphics cores, with previous experience in IP verification, particularly microprocessor core or interconnect/fabric Experience with verification environments using SVTB, UVM, or OVM Proficiency in HDL languages (System Verilog, Verilog, VHDL) and simulation tools Programming skills in C or C++ Ability to automate tasks using Perl, Python, or other scripting languages Experience with Uncore CPU features like Trace / Debug / Interrupts / Performance Monitoring is a plus Strong communication, problem-solving skills, and a verification-focused mindset. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

MIPS is seeking a skilled and motivated Design Verification Automation Engineer to develop advanced flows for CPU development. The candidate will build on existing modern methodologies to improve and support current infrastructure and create new solutions. They will work closely with lead developers in support of quality, efficiency, and predictability of execution through scripts, flows, and internal and third-party tools. The ideal candidate will have experience with CPU design verification development methodology and a solid background in software and flows. Required Skills: Python scripts and automation C, C++ Jenkins management Jira integration Familiarity with git or perforce LSF or Grid management Supporting Experience: Design Verification methodology Cadence or Synopsys verification solutions System Verilog, UVM CPU architecture, development, and software Database development Here s what you can expect from us: At MIPS, you ll be a member of a fast-growing team of technologists that are creating the industry s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure - you ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry s most experienced CPU engineers. An unlimited growth path - with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers. At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! More about us: MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Grow with us About this Opportunity: Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Verifier to join the Ericsson Silicon organization. You will work with dedicated engineers who are passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team defining verification strategies and implementing environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. You will do: - Define verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes - Implement verification environments and test cases to execute verification plans - Measure functional and code coverage metrics, driving towards completion targets - Debug RTL in conjunction with designers - Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive efficient solutions - Contribute to the continuous improvement of products, tools, and processes - Generate appropriate documentation You must have: - 5+ years of experience in FPGA/ASIC verification - Excellent knowledge of UVM and SystemVerilog - Ability to architect and create RTL testbenches from scratch - Strong knowledge of object-oriented programming - Experience with embedded software design and testing - Familiarity with modern FPGA device families and tools - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - An analytical approach and results-oriented mindset with the ability to deliver under pressure - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent Primary country and city: India (IN) || Bangalore Req ID: 768576

The Opportunity Were looking for the Wavemakers of tomorrow. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semis expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What youll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What youll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

We are looking for an FPGA Verifier to join the Ericsson Silicon organization. You will work with dedicated engineers who are passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team defining verification strategies and implementing environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. You will do: - Define verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes - Implement verification environments and test cases to execute verification plans - Measure functional and code coverage metrics, driving towards completion targets - Debug RTL in conjunction with designers - Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive efficient solutions - Contribute to the continuous improvement of products, tools, and processes - Generate appropriate documentation You must have: - 5+ years of experience in FPGA/ASIC verification - Excellent knowledge of UVM and SystemVerilog - Ability to architect and create RTL testbenches from scratch - Strong knowledge of object-oriented programming - Experience with embedded software design and testing - Familiarity with modern FPGA device families and tools - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - An analytical approach and results-oriented mindset with the ability to deliver under pressure - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Hi All, We are having opportunities for Design verification lead with SOC Verification Exp for Hyderabad location Exp: 8+ yrs Loc: Hyd Skills: Soc Verification, UVM, OVM, Verilog, System Verilog

We are looking for Senior SOC Verification Engineers for the Hyderabad location. 1) SOC Verification 2) SV UVM 3) DDR, PCIe, Ethernet. Interested candidates, Kindly Share with me your updated profile with Naveen.a@modernchipsolutions.com

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Software engineer II Work Location : Ahmedabad Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day Job Summary: Please send CV to K Madhu Prasad kmadhup@cadence. com We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. As part of this highly talented team, the candidate will develop verification environment and implement test features for Verification IP tools. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation. Job responsibilities: Responsible for the design, development, and verification of VIP. Experience and Technical Skills required: 2 to 4 years or equivalent relevant experience Proficiency in functional verification using SV/UVM and strong debugging skills. Strong Digital Electronics and Programming fundamentals. Hands-on knowledge of C/C++/Scripting. Working experience on PHY Interface for the PCI Express (PIPE), USB4, PCIe, DisplayPort will be a strong plus. Self-motivated individuals with strong analytical and communication skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent Behavioral skills required. Must possess strong written, verbal and presentation skills. Ability to establish a close working relationship with both customer peers and management. Explore what s possible to get the job done, including creative use of unconventional solutions. Work effectively across functions and geographies. Push to raise the bar while always operating with integrity. K Madhu Prasad kmadhup@cadence. com We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Software Engineer ( Development and verification of VIP ) Location: Bangalore / Ahmedabad Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. As part of this highly talented team, the candidate will develop, implement, and test features for the next generation of verification IP tools. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation. Job responsibilities: Responsible for the development and verification of VIP . Experience and Technical Skills required: 8 + years or relevant years of domain experience. Proficiency in functional verification using SV/UVM and strong debugging skills. Hands-on knowledge of Python/Scripting. Working experience on memories like HBM, LPDDRR, GDDR and DDR. (HBM, GDDR knowledge is plus) Prior VIP usage and development experience is a plus. Strong Digital Electronics and Programming fundamentals. Self-motivated individuals with strong analytical and communication skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity kmadhup@cadence. com Madhu We re doing work that matters. Help us solve what others can t.

Strong in digital design. Skills in ASIC/FPGA verification(directed test or SV/UVM) A good knowledge of simulation flow. Good scripting knowledge Perl/python Share your Resume to mansoor@hisoltech.com

About Marvell . Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers specifications, whether they re a major telecom organization or automotive company, etc. What You Can Expect - Individual contribution for the block, SoC, and subsystem-level verification. - Develop a test bench, test plan, and design a verification environment at the block and full chip levels. - Technically, lead junior engineers. What Were Looking For - Must have a good digital logic and the fundamentals of digital design verification. - The candidate must have excellent skills in digital logic verification and hardware description language - Must have worked on SoC, subsystem-level verification. - Knowledge in object-oriented programming using languages such as SystemVerilog and UVM methodology is an added advantage. - Must be familiar with verification test planning, test execution, and sign-off for the verification activity. - Must have good experience in using simulation tools and proficiency in simulation debug techniques. - Strong knowledge/experience in building the verification environment. Must have hands-on knowledge of test-bench development and automation, bug tracking, and regression mechanisms - Should be able to act as the team lead to determine methods and procedures for new assignments and coordinate activities of other team members to ensure successful project completion. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Experience with OVM/UVM/VMM/Test Harness, developing assertions, checkers, coverage, and scenario creation.,min 2 to 3 SoC Verification projects.developing test and coverage plans, verification environments, and validation plans,

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

NVIDIA needs a Senior Custom SOC/IP Verification Engineer for next-gen solutions. Seeking hard-working individuals to build life-changing custom SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: Lead ASIC design verification for various processing blocks in a SOC, including planning, execution, Coverage and methodology development. Collaborate with multiple teams (Architecture, SW/FW, Design, Modeling, Emulation, Post-Silicon Validation) to ensure comprehensive verification plans. Support engineering teams in delivering solutions for purpose-built ASICs and collaborate with IP development teams for IP identification, selection, and licensing. Analyze SOC and IP architecture, develop verification plans, and establish performance metrics. Work with partners in a co-development environment during development, debug, and bringup. Plan tests, achieve coverage closure, and enable customer TB infrastructure. Validate use cases for power-on and boot requirements. What We Need To See: Proficient in design verification tools like Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal. Consistent track record of first-pass success in ASIC Development. Holds a B. S. or M. S. degree in Computer Engineering or Electrical Engineering, with 7+ years of experience in ASIC, IP, or SoC design verification. Skilled in handling mixed language UVM and C++ testbenches, interpreting functional specs, and building comprehensive test plans. Experienced in developing tools and infrastructure using Perl or Python, with a strong background in AMBA protocols (AXI, ACE, CHI, ATB). Hands-on experience with subsystems in new technologies like ARM CPU, LPDDR, HBM, GPUs, DLA, PCIe, and Network on chip, including performance verification. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IOs and many other leading technologies deployed in our Tegra chips. What you will be doing: You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IPs and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit: Architect the testbenches and craft verification environment using UVM methodology Define test plans, tests and verification infrastructure for modules, clusters and system Build efficient and reusable bus functional models, monitors, checkers and scoreboards Implement functional coverage and own verification closure Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust What we need to see: You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs: CPU verification, Memory controller verification, Interconnect verification High Speed IO verification (UFS/PCIE/XUSB) 10G/1G Ethernet MAC and Switch Bus protocols (AXI/APB) System functions like Safety, Security, Virtualization and sensor processing Experience in the latest verification methodologies like UVM/VMM Exposure to industry standard verification tools for simulation and debug is a requirement Exposure to Formal verification would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate with e xcellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If youre creative and independent, with a genuine real passion for technology, we want to hear from you. #LI-Hybrid

Job Description Must have: Must Have Required Expertise: Should be able to build test plan, tests, coverage assertions from Specification. Architect and build testbench and testbench components. Good in UVM,SV,C SVA. Familiar with industry protocols, such as AXI, APB, AHB, PCIe, SoC. Very good in debugging. Worked with industry standard EDA tools Synopsys, Cadance simulators and debugging tools. Good to have skills: Experience with scripting and automation. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS and a proactive approach to automation. Exposure to SOC verification, Formal verification methodologies.