970 Uvm Jobs - Page 14

IP Verification Engineer -SoC Verification Engineer -Design verification Engineer- C Based System Verification engineer) experience: 8+ years location : Cambridge, United Kingdom, immediate joiners preferred Onsite opportunity JD: Responsibilities: Strong verification experience with knowledge of SystemVerilog, UVM System verification (C based) experience is a must. Good knowledge of testplan creation and tracking. Low-level programming experience including C and Assembler. Experience with full verification flow including coverage closure. Experience with ARM-based designs and/or ARM System Architectures AXI, CHI protocol knowledge,

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system levels, Test case coding and debugging, FC coding and analysis, and achieving quality metric goals and regression management. To be considered for this position, you should have a BS/BE in EE with 7+ years of relevant experience or an MS with 6+ years of relevant experience in IP cores verification and/or SOC verification. You should possess experience in developing HVL-based test environments, creating and implementing test plans, and extracting verification metrics like functional coverage. Additionally, you must have proficiency in HVL coding for Verification and hands-on experience with industry-standard simulators such as VCS, NC, MTI, along with relevant debugging tools. Exposure to verification methodologies like UVM/VMM/OVM is essential, and familiarity with HDLs such as Verilog and scripting languages like Perl is highly desired. A basic understanding of functional & code coverage, exposure to IP design and verification processes including VIP development, and good written and oral communication skills are crucial for this role. You should also be able to demonstrate strong analysis, debugging, problem-solving skills, and be self-driven. Join our Silicon IP business, where we focus on integrating more capabilities into an SoC faster. Synopsys offers the world's broadest portfolio of silicon IP, pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. We aim to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and bring differentiated products to market quickly with reduced risk. At Synopsys, we are at the forefront of innovations that reshape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our advanced technologies for chip design and software security power these breakthroughs. If you are passionate about innovation, we look forward to meeting you.,

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans.

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275

PMTS - GFX Verification Technical Lead Role: We are currently seeking a highly skilled Principal Member of technical staff (PMTS) Verification engineer for GFX top level end-to-end verification. Responsibilities: In this role, he/she would be the technical lead responsible for driving content, quality and debug throughput of top-level debugs coming from simulation, emulation, and post-silicon debugs. Working with architects and design leads and driving quality test plans Developing verification infrastructure and needed improvements Developing content strategy for quality. Driving DV closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and debug throughput. Helping management with risk assessment on features, quality, and schedules Working with sub-system DV leads to identify potential areas of formal verification Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute verification experience and system knowledge. Experience with advanced verification methodologies and languages like UVM, system Verilog. Familiarity with all Design areas and tools and confirmed understanding of design/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering #LI-NS1

Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Experience 8- 10 years Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs

Job Title Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs Experience 4-5 years

Tasks: Verificationof SoCs, automotive ASICs, subsystems, IPs. Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans Develop verification environments from scratch Create VIP Integration of VIP ( Verification-IP ) Measure and analyze regression results Continuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement: 5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM. Sound knowledge of constrained random verification, UVM/OVM Sound knowledge in System Verilog. Experience of developing functional coverage code, coverage analysis. Experience of developing verification environments from scratch is desirable. Good hands on experience with cadence/Synopsys/Mentor tools. Exposure to configuration management, bug tracking tool etc. Knowledge of scripting language, Perl TCL etc. Good experience with AMBA protocols Working knowledgeon ARM processor-based subsystem/SoC verification Formal verification experience is a desirable but not must. Must have been a part of one or more ASIC/SoC tape outs. Knowledge of VHDL/VERILOG. SPECMAN knowledge is a desirable but not must.

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise - VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications Bachelors or Masters degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related fie

Job Description Summary We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer. RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop C testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience

Job Description Summary We are looking for an expert AMS Verification Engineer that is familiar with the complete flow/methodology and can establish a modern AMS verification environment in a high-paced start-up. Responsibilities Review existing company designs and understand communication standards Establish a state-of-the-art AMS verification environment Co-develop an AMS verification plan with DSP/Digital/Analog teams from chip specification Execute plan and debug issues with team Develop test benches and models Provide feedback to design teams for AMS netlist optimization Expand and monitor AMS verification coverage and drive schedule timeliness Assist with debug simulations for silicon bring-up as necessary Create reports and documentation of AMS verification results and coverage Minimum Qualifications PhD/MSEE with at least 5 years domain expertise and have prior circuit design experience Proven record of AMS verification for mixed-signal SOCs in example fields such as: Ethernet/PCIe/MIPI DSL/DOCSIS 11, GSM/LTE Ethernet/PCIe/MIPI DSL/DOCSIS 11, GSM/LTE Expert at one of Cadence AMS-D/Incisive/Xcelium, Mentor Symphony, Synopsys VCS-AMS Able to model analog circuits in Verilog / Verilog-A / Verilog-AMS / SystemVerilog and adept with simulations in Explorer/Assembler Experience in solving Analog-Digital tool interaction issues and simulation slowness Experience in solving Analog-Digital tool interaction issues and simulation slowness Good written and verbal communication skills Additional experience in the following preferred: PERL, Python UVM, UPF Analog timing verification and .LIB generation DSP based data communication systems design ISO 26262 FuSa certification (SC-AFSP)

Key Responsibilities Architect and implement System Verilog/UVM-based testbenches and verification environments for analogmixed signal blocks and SoCs. Develop VerilogA , RealNumber Models (RNM) , WREAL models, and support cosimulation with SPICE for behavioral accuracy. Execute verification of highspeed serial protocols including PCIe , USB 3 , MIPI CSI/DSI , using constrainedrandom stimulus, assertions, monitors, functional coverage. Utilize tools like PrimeSim XA (VCS AMS) to run mixed-signal regressions and VerilogA analog simulations. Collaborate closely with digital, analog, synthesis, timing, and silicon bring-up teams to ensure spec traceability, debug failures, and validate first-pass silicon performance. Write thorough verification plans , track coverage closure, debug RTL/AMS models, document results, and drive continuous improvement of methodologies. Qualifications & Skills Bachelors/Masters in Electronics/Telecommunication, Computers, Electrical . 5+ years of mixed-signal/AMS verification experience; SoC-level IP/subsystem/SoC verification preferred. Deep proficiency in System Verilog , UVM , assertions, functional coverage, OOP testbench design. Strong expertise in VerilogA , RNM/WREAL , and building analog behavioral models Simply. Hands-on experience with PrimeSim XA/VCS AMS , Cadence Spectre/Xcelium, Synopsys AMS toolchains.

About Client Hiring for One of the Most Prestigious Multinational Corporations! Job Description Job Title : VLSI Front-end Services Practice Head/ VLSI Director Engg Required skills and qualifications : Create differentiated VLSI Services offerings, capabilities, and talent to exponentially grow VLSI services business. Ability to engage with customer design managers in technical discussions and secure design wins Create strong VLSI technical teams through training/upskilling and focused hiring. Mentor the VLSI team to ensure their skills are continuously advanced & aligned to customer/industry needs. Build strong customer relationships and deliver VLSI services projects. Create differentiated proposals to win new projects. Work within inhouse resourcing teams and external partner ecosystem to staff and ramp-up VLSI team based on customer needs Strong technical expertise in ASIC frontend development: logic design & verification (including UVM), power specification (e.g. UPF), timing specifications (SDC), formal verification and emulation Hands-on expertise with commercial EDA tools from Synopsys, Cadence or Siemens Intimate familiarity with Verilog and standard design formats (LEF, DEF, SPEF, etc.) Good industry connects with EDA tool companies, foundries and Tier 1 semiconductor companies Exposure to ASIC-package codesign a plus. Create and leverage VLSI partner ecosystem for expanding offerings and talent Stay updated on semiconductor industry trends and competitor activities to refine the strategy accordingly and gain customer mindshare. VLSI services Strategy, Business Plans and roadmaps SoW and MSA reviews Roles and Responsibilities: Drive VLSI services strategy, offering, capabilities, and talent creation and scaling Own and meet the VLSI services business growth Collaborate with academia, partners and talent teams to grow VLSI talent Create differentiated design methodologies, offerings and solution demos to showcase at industry events Collaborate with Presales and Sales teams to develop compelling customer propositions and sales collateral Ability to engage confidently at senior levels within customer organizations Review and ensure smooth delivery of VLSI services engagement Utilize industry trends, competitive insights to enhance sales strategies and provide input to offering owners. Excellent stakeholder management and client facing skills Excellent communication and analytical skills Qualification : Any Graduate or Above Relevant Experience : 15 to 24 yrs Location : BANGALORE/HYDERABAD CTC Range : 60 TO 80 LPA Notice period : ANY Mode of Interview : Virtual Mode of Work : In Office Sana.F Staffing analyst - IT recruiter Black and White Business solutions PVT Ltd Bangalore, Karnataka, INDIA sana.f@blackwhite.in I www.blackwhite.in +91 8067432462

Job Description Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in SystemVerilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, SimVision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers

Design Verification Engineer (Senior Level - 5+ years experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 5+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

SoC Verification Engineer SoC Verification Engineer >> SoC Verification Engineer Post SoC Verification Engineer Required Experience 1 to 3 years Location: Bangalore,Delhi NCR,Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Must haves: Worked on IP level verification environment 1 to 3 years of experience Good experience with Verilog, System Verilog and UVM Experience with verification for protocols like AXI or AHB Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB Excellent Team Player Good To Have Experience of SOC Verification Experience of Formal verification Experience on verification of automotive protocols Email your resume to careers@truechip.net and mention position/location in the subject,

You will be joining our team as an experienced UVM and GenAI Engineer, focusing on developing innovative solutions using Generative AI to automatically generate testbenches for complex digital designs. Your responsibilities will include collaborating with design and verification teams, implementing Generative AI algorithms, designing UVM-based testbenches, and integrating AI-generated testbenches into the verification flow. You will also be required to stay updated with the latest developments in UVM, GenAI, and digital design verification, participate in code reviews, and contribute to enhancing the team's verification methodologies. To qualify for this role, you should hold a Bachelor's/Master's degree in Computer Science, Electrical Engineering, or a related field, along with at least 6 years of experience in digital design verification with a focus on UVM-based testbenches. Proficiency in UVM, SystemVerilog, digital design principles, AI/ML frameworks, programming languages like Python, C++, and systemVerilog, as well as experience with version control systems like Git, are essential. Strong problem-solving skills and the ability to work both independently and collaboratively are also key requirements. It would be advantageous if you have experience with Generative AI algorithms, digital design languages such as VHDL or Verilog, cloud-based AI platforms like AWS SageMaker or Google Cloud AI Platform, and Agile development methodologies. In return, we offer a competitive salary and benefits package, the opportunity to work on cutting-edge AI technology and digital design verification, a collaborative work environment, professional development opportunities, and flexible working hours with remote work options. If you are a motivated individual with a passion for UVM, GenAI, and digital design verification, we encourage you to submit your resume and a cover letter detailing why you are the perfect fit for this role.,

Dear Candidate, We are hiring for Top MNC!! Location: Pune Work Mode: Hybrid-General Shift Contract: 1 Year Required Skills As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary. If interested, please share your updated cv to arthie.m@orcapod.work

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experience with ML/AI applications in hardware design, verification and Low Power (e.g., formal verification with ML, coverage closure with ML). Experience with verification methodologies (UVM, OVM). Experience in data preprocessing and feature engineering, hardware architecture and microarchitecture. Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Excellent programming skills in Python or C++. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Research, design, and implement ML/AI algorithms techniques for various verification tasks, including test case generation, coverage analysis, bug prediction, and performance optimization. Develop and maintain tools and scripts for data collection, pre-processing, model training, and evaluation. Analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends. Build and train ML models for various verification applications, such as anomaly detection, pattern recognition, and prediction. Evaluate model performance and iterate to improve accuracy and efficiency. Participate in verification planning and develop test plans that incorporate ML/AI-driven techniques. Execute verification tests and analyze results to identify bugs and coverage gaps. Develop and maintain verification tools and scripts to automate verification tasks.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience with one scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Prior internship or co-op experience in a hardware design or verification role within the semiconductor industry. Experience developing and maintaining verification testbenches, test cases, and test environments. Experience through coursework or academic projects involving simulation, testbench development, or formal verification techniques. Familiarity with industry-standard verification methodologies such as UVM (Universal Verification Methodology) or OVM (Open Verification Methodology), even if at a foundational level. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Provide test plans including verification strategy, environment, components, stimulus, checks and coverage, and ensure documentation is easy to use. Run pre-defined test cases and test benches, analyze simulation results, and identify discrepancies or failures. This includes debugging basic issues and collaborating with senior engineers to resolve more complex problems. Under guidance, contribute to the development of simple verification components such as monitors, checkers, or basic test sequences, and assist in maintaining existing verification infrastructure. Record test results, document bugs and their replication steps, and provide regular updates on verification progress to the team, highlighting any critical issues or roadblocks.

Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience. 4 years of experience with Design Verification. Experience with System Verilog and Verification techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience creating/using verification components and environments in methodology (e.g., VMM, OVM, UVM). Experience with scripting languages like Perl or Python. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design verification leads and design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM and/or formally verify designs with SVA and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with Power Management. 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Interconnect Protocols (eg. AHB, AXI, ACE, CHI, CCIX, CXL). Experience in low-power design verification. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Develop cross language tools and verification methodologies. Create and enhance constrained-random verification environments using SystemVerilog and UVM.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases,and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with low power, debug, Gate Level Simulation (GLS), formal verification. Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs. Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools. Debug tests with design engineers to deliver functionally correct design blocks. Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs. Be the primary point of contact for functional verification of the IP for cross-functional teams.

Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark. Experience with GPU architecture and AMBA Bus protocols like AHB/AXI/ACE. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience with performance verification of ASICs and ASIC components. Experience with verification of low power techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Be part of a team to verify complex digital design blocks (e.g., CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.