970 Uvm Jobs - Page 12

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

As an AMS Verification Engineer, you will play a crucial role in ensuring the successful verification of Analog Mixed Signal designs. With a minimum of 5 years of experience in this field, you will be responsible for developing and executing verification plans, creating testbenches, and collaborating with design teams to guarantee that designs meet specifications. Your key skills will include strong RNM modeling proficiency, hands-on experience with Cadence AMS/DMS flow, familiarity with SystemVerilog and Verilog-AMS, and a solid understanding of analog and mixed-signal design principles. Additionally, you should have expertise in UVM, the ability to debug AMS modeling issues, and experience with basic scripting and automation. Your responsibilities will involve building and maintaining SystemVerilog real number models, verifying AMS/DMS IP/chip functionality, and ensuring effective communication and documentation throughout the verification process. By working closely with both analog and digital design teams, you will contribute to the successful verification of complex AMS designs. If you are a detail-oriented verification engineer with a passion for analog mixed-signal design and a strong background in AMS verification, this role offers an exciting opportunity to further your career in a dynamic and collaborative environment.,

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will conduct coverage analysis to ensure the validation's completeness, implement assertion-based verification to guarantee functional robustness, and collaborate across teams to align design and verification milestones. Your tasks will also involve working with RAL to validate register-level behaviors, creating testbenches for simulation, and optimizing performance efficiency. If you have 6 to 10 years of relevant experience and are eager to make a significant impact in chip-level verification, we encourage you to apply for this permanent position. This is a Work from Office opportunity located in Siruseri, Chennai. Immediate joiners are preferred. Don't miss this chance to be part of a dynamic team and contribute to cutting-edge chip design projects. Send your resume to Venkatesh@coventine.com or contact us directly to explore this exciting career opportunity. Join us in shaping the future of hardware design and advancing your career in the field of design verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

The position of Technical Lead ASIC Design Verification requires the candidate to have direct experience in managing a 4-10 member engineering team and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements). The role involves Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customer products. The incumbent will lead an IP Verification team and provide technical leadership to the Design Verification team. Effective team management, coaching, mentoring, and career planning are essential responsibilities. The incumbent must lead management and customer reviews for multiple projects and develop/modify scripts to automate the verification process. The candidate should have a minimum of 6 years of experience in System Verilog HVL and OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertion, checkers, coverage, and scenario creation is required. Experience in executing at least 2 to 3 SoC Verification projects, developing test and coverage plans, verification environments, and validation plans is necessary. Knowledge of industry-standard protocols like Ethernet, PCIe, MIPI, USB, or similar is expected. The candidate should have at least 1 year of experience in handling a team of 5 to 10 engineers. Defining/deriving scope, estimation, schedule, and deliverables of proposed work, ensuring resource compatibility, and working with customers through acceptance of deliverables are also key responsibilities. This is a Work from Office job, and the incumbent should have the willingness and experience to lead and mentor junior engineers. The educational background required for this position is B.E./B.S./B.Tech/M.S./M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering. eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services with a proven track record of over 25 years. With a team of over 2500+ engineers, the company has been instrumental in developing over 500+ products and 40M deployments in 140 countries. eInfochips offers Silicon Engineering, Embedded Engineering, Hardware Engineering & Digital Engineering services and is recognized as a leading Semiconductor service provider by NASSCOM, Zinnov, and Gartner.,

As a Verification Engineer, you will be responsible for utilizing your 2+ years of experience in ASIC/FPGA verification to develop test plans and verification strategies that thoroughly and effectively validate requirements and specifications. Your expertise in developing SV + UVM based verification environment components, such as agents/UVCs, scoreboards, predictors/reference models, and creating tests using constrained random based test sequences will be essential for success in this role. Your role will also involve implementing functional coverage, identifying and resolving coverage gaps, and writing tests to ensure comprehensive verification. Additionally, you will have the opportunity to contribute to code coverage activities and enhance the overall verification process. To excel in this position, you should possess strong problem-solving skills and be capable of working both independently and collaboratively as part of a team. Your familiarity with scripting languages like GNU make, Perl, and Python will be advantageous, along with any experience in FPGA verification compliance to DO-254 standards. Exposure to verifying DSP blocks, such as filters, adders, multipliers, and limiters using fixed-point operations, will further enhance your contributions to the verification process. Overall, your ability to communicate effectively, both verbally and in writing, will be crucial in ensuring successful collaboration and project outcomes. If you are a trained fresher with a passion for verification engineering, you are also encouraged to apply and contribute your skills to our dynamic team.,

5+y in processor verification Proficiency in UVM SystemVerilog for developing verification environments,testbenches Validate ARM M-series,RISC-V processor designs C programming for processor-level test EDA for simulation,debugging,coverage analysis

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 3-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #LI-EDA #LI-Hybrid #DVT

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise -2+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

Our Team: Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading-edge products. The Wireless analog/digital and LoRa System teams located in our Neuchtel and Grenoble offices have unique expertise in system level solutions for Low Power Wireless Area Network (LPWAN) products. These teams are the worlds leaders for long range, low power, battery powered, wireless communication. The Semtech expertise cover a unique field from the antenna, analog & digital IC design, low power system, protocol, and cloud-based solutions. You will be part on the journey of the new LoRa and LoRaWAN System architecture. Job Summary: We are seeking an experienced and dynamic SoC Verification Manager to lead our verification team. The successful candidate will manage a team of up to 5 verification engineers, overseeing the verification of RTL designs to ensure the highest quality and performance of our wireless SoCs. This role involves team technical leadership, project management, and hands-on verification tasks. Responsibilities: Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback.(20%) Ensure the definition and implementation of test and verification plans.(20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification.(10%) Identify and resolve verification issues and bugs, ensuring timely project delivery.(10%) Continuously improve verification processes, methodologies, and tools.(10%) Manage project schedules, resources, and deliverables to meet deadlines.(10%)Lorawa Oversee the writing and debugging of SystemVerilog assertion.(10%) Minimum Qualifications: 8+ years of relevant experience in SOC verification. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g., VCS, QuestaSim). Experience with SoC designverification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Board Design.

The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route.: Experience: 1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience:Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the >

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification Experience: 3-5 Years

Role & responsibilities To play the role of Verification engineer at the Block level verification. Develop verification test plans from design specifications. Development of test environments using System Verilog and UVM verification methodologies. Integration with RTL and basic simulation bring-up for the design. Create multiple test cases as per test plan and launch regressions. Generate Code/Functional coverage, analyze coverage results and correlate with the test plan. Working the design team members to identify and quickly resolve problems with the design. Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenge Preferred candidate profile Domain Expertise : AHB, AXI, PCIe, USB and Ethernet. Languages (must): Verilog, system Verilog Methodologies (One of them is must): OVM/UVM/VMM EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog Experience in developing Test Bench components in both block level and SOC level. Experience in Creating test plan and Writing test sequence. Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable) Good analytical and problem-solving skills Excellent written and verbal communication in English. Good teamwork and the desire to excel in a competitive environment. Qualification: Bachelor's Level Degree (ECE, EE / preferred specialization) with more than 9 years of work experience

Job Requirements Engineer must possess string understanding od Design Verification with 5+ Year of exp. Engineer must possess strong understanding of SystemVerilog, UVM.

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as we'll as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B. S. /M. S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3. 0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc. ), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable.