970 Uvm Jobs - Page 11

You will be working as a Verification Engineer at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering department. Your primary responsibility will be to take ownership of SoC Debug DV, which includes tasks such as Crash reset, Trace, debug infrastructure, among others, throughout the project lifecycle. Your key responsibilities will include understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and verification infrastructure, and ensuring the correctness of the design. You will collaborate with other members of the verification team to analyze, develop, and execute verification test cases, offering relevant solutions to issues. Additionally, you will work closely with architects, designers, and pre and post-silicon verification teams. To be successful in this role, you should hold a B.E/B.Tech/M.E/M.Tech degree in Electronics with at least 7 years of experience in the verification domain. You must possess a good understanding of Soc level verification testbench and flows, as well as working knowledge and design understanding of Debug architecture of a SoC, including Crash flow, JTAG, Trace, triggers, monitors, Scandump, etc. Exposure to Power aware simulations and Gate Level simulations is desired, along with expertise in Verilog, System Verilog, and UVM based environments for processor-based Soc level verification. A solid grasp of AHB/AXI & ATB-AMBA protocols is also essential. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com for support. It's important to adhere to all applicable policies and procedures, including security requirements for protecting confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking a job directly at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions, and any such submissions will be considered unsolicited. For further information about this role, please contact Qualcomm Careers directly.,

Role Overview As a Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contribute to verification methodology improvements and best practices. Perform regression setup, coverage analysis, and issue tracking. Deliver high-quality, first-time-right silicon. Required Skills Strong experience in IP/SoC verification using SystemVerilog/UVM . Solid understanding of verification methodologies and simulation flows. Hands-on with tools like VCS, Questa, Verdi, SimVision, etc. Experience with standard bus protocols like AXI, AHB, PCIe, USB, etc. Good debugging skills using waveform viewers and log analysis. Experience in writing assertions and functional coverage models. Knowledge of scripting (Python, Perl, TCL) is a plus. Strong communication and leadership abilities. Preferred Qualifications Experience with formal verification, assertion-based verification (SVA). Exposure to low-power verification and UPF flows. Familiarity with safety/security standards (e.g., ISO 26262, DO-254). Experience working with emulation platforms and FPGA prototyping. Location: Bangalore / Hyderabad / Pune Experience: 815 Years Notice Period: Immediate to 30 Days Company: ADV Logics – Empowering Next-Gen VLSI Innovation

Roles and Responsibility Experience in Subsystem or SoC verification and experience including C based test cases development Experience in IP verification using UVM Exposure to all stages of verification: requirements collection, verification plans, testbench implementation, test case development and coverage closure Good Problem Solving and Debugging skills. Experience with ARM-based designs, AMBA APB, AXI, CHI, and Cache coherency concepts Porting peripheral driver software for SoC test cases. Experienced in GLS, DFT/DFD, Power Aware verification techniques

Roles and Responsibility Senior CPU System Verification Engineer Role Overview: Focused on validating CPU subsystems at SoC level, including coherency, interconnect protocols, and system-level features. Key Responsibilities: Architect and lead UVM-based SoC verification environments Define SoC-level verification plans and coverage strategies Drive verification of memory subsystems, MMU, and coherency protocols Debug and resolve critical functional issues and performance bottlenecks Mentor junior engineers and review test/coverage implementation Required Skills: 8+ years of experience in system-level verification Strong knowledge of SystemVerilog, UVM, and SVA Deep understanding of interconnect protocols (AXI, CHI, ACE) Proven ability to debug simulation failures and track coverage metrics Experience with regression infrastructure, scripting, and waveform tools

Roles and Responsibility Senior IO-MMU Verification Engineer Role Overview: Responsible for functional verification of IO-MMU units, focusing on translation, protection, and system interaction with DMA/IP blocks. Key Responsibilities: Develop UVM-based environments for IO-MMU verification Create tests for virtual address translation, permissions, and fault injection Verify compliance with protocols like PCIe ATS, PRI, and ARM SMMU Collaborate with SoC-level teams for system integration and validation Drive functional and code coverage closure Required Skills: 8+ years in verification of memory or IO subsystems Expertise in UVM, SystemVerilog, SVA Strong debugging and protocol knowledge (AXI, PCIe, SMMU) Experience with constrained-random and assertion-based verification Familiar with trace analysis and formal verification integration

Design Verification Engineer (5 + years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement e & responsibilities

Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead project execution Good to Have: Scripting and automation (Perl/Python/TCL) Experience with UPF simulations , GLS , and Formal Verification Exposure to SoC-level verification Strong communication and leadership abilities

Job Description: We are looking for skilled Design Verification Engineers with 5-10 years of strong experience in the semiconductor domain. Ideal candidates will have hands-on experience in SystemVerilog (SV) and UVM , along with a solid understanding of SoC/IP level verification , GLS , and CPU verification . Key Skills Required: SystemVerilog (SV) UVM (Universal Verification Methodology) SoC/IP Level Verification GLS (Gate-Level Simulation) CPU/Sub-system Verification High-speed interface protocols: PCIe, DDR, Ethernet Requirements: Immediate to 30 days joiners only Willing to work from office (Bengaluru or Hyderabad) Strong debugging and problem-solving skills Excellent communication and team collaboration abilities

Strong in digital design. Skills in ASIC/FPGA verification(directed test or SV/UVM) A good knowledge of simulation flow. Good scripting knowledge Perl/python Apply &Share your Resume to mansoor@hisoltech.com

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Design Verification Engineer (5+ years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer based in Siruseri, Chennai. In this role, you will have the opportunity to work closely with a top-tier client and play a pivotal role in developing next-gen chip-level verification environments utilizing System Verilog and UVM methodologies. This is a full-time position that requires you to work from the office. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. Your tasks will include developing verification test plans based on detailed design specifications, constructing UVM-based simulation environments using System Verilog, analyzing coverage to ensure completeness, implementing assertion-based verification for functional robustness, validating register-level behaviors with RAL, collaborating across functions to synchronize design and verification milestones, and creating testbenches for simulation and performance efficiency. The ideal candidate for this role should have a minimum of 6 to 10 years of experience in design verification. You should be well-versed in System Verilog, UVM, and ASIC verification methodologies. If you are passionate about making a significant impact in chip-level verification and are ready to contribute to cutting-edge projects, we encourage you to apply for this position by sending your resume to Venkatesh@coventine.com or by contacting us directly. Join our team at Coventine Digital Private Limited and be part of a dynamic environment where your skills and expertise in design verification will be valued and recognized. Take the next step in your career and explore the exciting opportunities that await you in the field of chip design and verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,

We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise - VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups etc Qualifications Bachelors or Masters degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related fie

Digital Electronics Testing Internship Hyderabad, Telangana, India Interns/Temp Intern Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration. Engineer your future with us!. Play Video Job Description Category Interns/Temp Hire Type Intern Job ID 7073 Remote Eligible No Date Posted 13/07/2025 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Internship Experience: At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide and having fun in the process! Youll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today s innovations and spark tomorrow s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive both at work and beyond. What You ll Be Doing: Writing constrained-random System Verilog test benches using UVM/VMM. Examining functional, assertions and code coverage. Debugging RTL and gate-level simulations failures. Testing products and flows to ensure quality and reliability. Verifying fixed issues to confirm effective resolution. Collaborating with the engineering team to identify and address technical challenges. Documenting test cases, procedures, and results for transparency and learning. Providing feedback for continuous tool and process improvements Participating in team discussions to brainstorm solutions and share innovative ideas. What You ll Need: Currently pursuing / recent graduate of B-Tech or M-Tech in Electronic Engineering, Computer Science, or a related field (penultimate or final year is preferred). Strong analytical and problem-solving skills. Basic knowledge of digital electronics concepts. Excellent communication skills. Meticulous attention to detail. Ability to work collaboratively in a team environment. Proactive attitude and eagerness to learn. Key Program Facts: Program Length: 12 months Location: Hyderabad, India Working Model: On-site Type of Internship: Industrial Placement Full-Time/Part-Time: Full-time Start Date: July/August2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

In your new role you will: 10+ years of Digital Verification experience and a deep understanding of all technical aspects of Verification, including 2+years of technical leadership activitie s Masters/bachelor s in electrical/Electronic Engineering or ComputerScience. Familiarity with version-controlling (eg, Git/Bitbucket, ClearCase,CVS, SVN) and bug-management systems (eg, JIRA). Good to have: Knowledge of ISO26262 and ISO21434. Outstanding Expertise in digital verification and all tasks needed to achieve design verification closure, including state of the art tools and methodologies (SV-UVM, Xcelium, vManager, Certitude, etc) Verification experience in Graphics IP design, cryptographic hardware IP design is a plus. A sense of urgency for upcoming innovation in the field of Verification Proven leadership skills, with experience in coordinating activities,providing technical guidance, and mentoring junior engineers. Self-motivated, flexible, good communication with interpersonal skills and is a good team player who can work well with both internal and external partners Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives A proven ability to solve problems with higher complexity by pro-actively involving expert networks You are best equipped for this task if you have: Digital verification of complex digital design IPs and Subsystems,ASIC and SoCs. Coordinate the overall digital verification activities such as verification planning, verification tracking and reporting, as well as requirement-based verification Collaborate with cross-functional teams, including concept, design to ensure high quality designs Hands-on contributor to digital verification either from scratch, or using legacy verification environments and flows Focus on reuse of the Verification Components to be implemented Identify and mitigate risks in dynamic projects, with pro-active communication to the project team Drive the enhancement of existing verification methodologies and flows, drive required innovation projects and get buy-in from management Foster process and efficiency improvements where applicable, as well as share your expertise to the other team members so that they can grow. As a technical lead inspire and mentor junior verification engineers while providing invaluable technical support and guidance to development teams and business partners We are on a journey to create the best Infineon for everyone.

Description Job Title: Sr. Engineer, Hardware Verification Job Location: Bangalore, India Job ID: AI2413 Job Description: As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ai s MLSoC . You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team. Minimum Qualifications: BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Preferred Qualifications: ML experience C/C++ Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Job Title: Sr. Engineer, Hardware Verification Job Location: Bangalore, India Job ID: AI2413 Job Description: As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ai s MLSoC . You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team. Minimum Qualifications: BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Preferred Qualifications: ML experience C/C++ Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

Title/Position: Senior Verification Engineer Location: PAN India Type: Fulltime Key Skills and Responsibilities: 5 to 15 years in IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI or UPF or DDR Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incisive Technical Documentation: Testbench Specification, Test Plan Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL Bachelors in Electronics Engineering is a minimum requirement Masters in Electronics or Computer Science Engineering is an added advantage Exposure to working in multi-national environment is required Excellent oral and written communication skills is a must. An attitude to learn and grow. Adaptability and flexibility are desired.

Design Verification with SV UVM

Job Title:DEVOPS- AWS Glue, KMS, ALB , ECS and Terraform/TerragruntExperience5-10YearsLocation:Bangalore : DEVOPS, AWS, Glue, KMS, ALB , ECS, Terraform, Terragrunt

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Job Description: We are looking for an experienced SoC DV Lead with a strong background in SoC verification and hands-on experience in writing C test cases for SoC-level DV. Key Responsibilities: Lead SoC DV activities from planning to closure Develop and debug C-based test cases for system-level verification Work closely with design, architecture, and firmware teams Perform coverage analysis and ensure comprehensive validation Guide and mentor junior DV engineers Key Skills: SoC-level design verification C programming for test development Debugging and problem-solving Exposure to UVM/SystemVerilog (preferred) Strong understanding of SoC architecture

Responsibilities: * Collaborate with cross-functional teams on bug resolution. * Ensure software compliance with functional requirements. * Develop verification environments using UVM/SV methodology.