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Design Verification Zilogic Systems

2.0 - 6.0 years

0 Lacs

karnataka

On-site

You should have a strong understanding of Design & Verification methodologies related to either Times or Untimed SW Models, RTL IP, VIPs, and UVM Env. It is essential to be familiar with verification tools such as Simulator and Synthesis. Proficiency in C/C++, System Verilog, UVM, SystemC, and RTL is required. Knowledge of standard protocol interfaces like AMBA, Automotive, PCIe, and USB would be beneficial. Strong written and verbal communication skills are necessary, along with the ability to work effectively both independently and as part of a team. A self-motivated attitude and a collaborative approach to teamwork are also important attributes for this role.,

Posted 3 months ago

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