Embedded C/C++ [Development experience in SOC platforms like iMX.8, FPGA Linux] Linux middleware and application development. Debugging skills on Embedded Linux. Yocto build environment.

Should have strong knowledge on Computer Hardware and Windows OS. Need to have rework knowledge related to motherboard and good understanding with electronic components. Must have experience in windows. .Knowledge and experience with kernel- mode debugging using Microsoft development tools (Visual Studio, WinDBG, etc.) Engineer should have Knowledge on CPU Cores, Intel DTT, Gaming core Performance Evaluation, hyper threading. Additonal knowledge related to Intel Innovation Framework and ATPG (Automatic test pattern generator)Python Scripting will be added advantage. Must have work experience in validating various domain ( like Graphics, PM, IPU,Sensor, Wi-Fi, BT, USB,TBT ,etc). Solid background in Pre/Post Silicon validation Ability to work independently and proactively. Good problem analysis and solving skills coupled with a strong drive to learn and teach others Required skills and qualifications Basic knowledge about technologies. Good communication skills What We Offer Flexible work environment, allowing for full-time remote work globally for positions that can be performed outside a HARMAN or customer location Access to employee discounts on world-class Harman and Samsung products (JBL, HARMAN Kardon, AKG, etc.) Extensive training opportunities through our own HARMAN University Competitive wellness benefits Tuition Reimbursement Access to HARMAN Campus Fitness Centre and Cafeteria An inclusive and diverse work environment that fosters and encourages professional and personal development.

SoC Verification Engineers (10+ Years) Full Time Posted 6 months ago Job Summary: We are seeking an experienced SoC Verification Engineer with over 10 years in the field to manage and direct verification projects. The ideal candidate should have extensive knowledge of AXI, AHB, and high-speed protocols and expertise in UVM-SV and C-based test development. You will be responsible for managing a team, troubleshooting SoC test issues, and ensuring effective testbench operations. Strong leadership, problem-solving abilities, and clear communication are essential for this role. Skill Set Requirements: 1. Protocols: Strong knowledge in AXI know how s of AHB Experience in any one or more of the high-speed protocols (PCIe, USB, DDR, USB, Ethernet, CXL, UCIe, and AHB) is a must. 2. Experience in UVM-SV, C-based test case development. 3. SV-UVM Based Testbench Development. 4. Prior experience in SoC verification is required. 5. Should have managed a team of size 7+ as well as hands-on experience in project execution. 6. Good experience in Scripting(PERL or PYTHON) Responsibilities: a) Guiding the team in SOC verification using UVM-SV and C-based test flow. b) Crafting verification tests using both C and SystemVerilog (SV), including managing the communication and synchronization between these languages to ensure thorough feature verification. c) Should be able to debug the SoC test failures. d) Should be able to lead a team of a minimum of 7 in size. e) Should be ready to work with teams in different time zones. f) Exceptional problem-solving and teamwork skills, with excellent communication abilities both verbal and written, and the aptitude to rapidly adapt and become proficient. Benefits: Competitive salary and performance-based bonuses. Comprehensive health benefits package. Work on cutting-edge technologies and impactful projects. Opportunities for professional development and career growth. Flexible work hours and remote work options available based on client s policy.

Software Engineers [BSP Firmware] Roles & Responsibilities: Develop, test and integrate device drivers for various devices on our high-performance platforms including Ethernet, I2C, PCIe, SPI, USB, NAND devices Customize BSP, boot code and device drivers Work closely with hardware engineers in board bringup Work closely with manufacturing teams for qualification through diagnostics packages Develop software solutions for high availability and redundancy Lead and mentor a team of high-performance engineers Interact with customers to gather requirements, design firmware and ensure quality of deliverables Interact with cross functional team including product management, hardware engineering, manufacturing, sales teams to design high-performance, cost-effective solutions for storage and switching platforms Qualifications: 10+ years of work experience implementing device drivers and BSP Experience working with cross functional teams including hardware engineering, manufacturing Strong knowledge of real time operating system concepts, multithreading, SMP Strong knowledge of C, Linux driver programming and kernel architecture Knowledge of Python Outstanding software debugging skills Experience using a full range of hardware test equipment like JTAG debuggers, I2C analyzer etc. Solid understanding of Ethernet PHYs, PCIe, USB, SPI, NAND, I2C and SDRAM Knowledge of Intel x86 architecture and BIOS/UEFI is a plus Bachelors or Master degree in ECE, CS, IT or EEE Excellent verbal and written communication skills Strong interpersonal, multitasking and organizational skills Ability to work under pressure.

Skills: . Device Drivers, Windows, c, c++, Kernel, Windbg,. Experience2 to 5 years. He/She should be part of Multi-Media Audio SW team. He/She should closely work with Device Drivers & DSP Firmware/Algorithms & SoC/IP teams to develop and deliver drivers for different audio interfaces. He/she should also very closely work with Domain/SW Architects to lead the design and development of key audio features. Preferred Experience. 2-5 years of work experience. Experience in system programming & windows device drivers development. Experience in Windows kernel programming. Experience in Windows device driver development. Experience in Windows drivers as WPF, WDM, KMDF, UMDF, Windows Internals & PCI Bus. Experience in tools like Windbg, Windows Debug Viewer, ETL, ReadWrite, Windows Logo & HLK, Oscilloscopes & Protocol analyzers like Lecroy USB etc. Experience in C, C++ programming & Data Structures. Experience in using IDEVisual Studio

SoC Verification Engineers (3 to 5 Years) Copy Full Time Posted 1 month ago Job Summary : We are seeking an experienced Verification Engineer , whose role includes creating and debugging test plans for protocols such as AXI, AHB, PCIe, USB, and others. Strong problem-solving abilities, excellent communication, and the capacity to work independently across various time zones. Skill Set Requirements : 1. Protocols : Strong knowledge in AXI know how s of AHB Experience in any one of the high-speed protocols (PCIe, USB, DDR, USB, Ethernet, CXL, UCIe) 2. Experience in UVM-SV, C-based test case development 3. Prior experience in test plan development for all the protocols worked. 4 . Prior experience in SoC verification is Must 5. Expected to have good knowledge in SoC level testbench involving SV-UVM and C-based flows . Responsibilities: a) Develop tests for SOC verification using UVM-SV and C-based test flow. b) C rafting verification tests using both C and SystemVerilog (SV), including managing the communication and synchronization between these languages to ensure thorough feature verification. c) Should be able to debug the SoC test failures. d) Should be ready to work with teams in different time zones. f) Strong problem-solving and teamwork skills, and strong verbal and written communication skills Capable of quickly ramping up and working independently under guidance Educational Qualifications: Degree in BTech/MTech Benefits: Competitive salary and performance-based bonuses. Comprehensive health benefits package. Work on cutting-edge technologies and impactful projects. Opportunities for professional development and career growth. Flexible work hours and remote work options available based on client s policy.

SoC Verification Engineers (5 to 8 Years) Full Time Posted 6 months ago Job Summary: We are seeking an experienced Verification Engineer with 5+ years of expertise in AXI and high-speed protocol s whose role involves developing and executing SoC verification test plans using UVM-SV and C-based flows, debugging test failures, and ensuring comprehensive coverage closure. Skill Set Requirements : 1. Protocols: Expertise in AXI Expertise in any one or more of the high-speed protocols (PCIe, USB, DDR, USB, Ethernet, CXL, UCIe) 2. Expertise in UVM-SV, C-based test case and testbench development . 3. E xperience in SoC verification is a must . 4. Expected to have good knowledge in SoC level testbench involving SV-UVM and C-based flows ; should be able to make changes based on the requirements. 5 Good debugging skills . 6 Familiarity with scripting(PERL or Python) . 7 . Prior experience of test plan development for all the protocols worked. Responsibilities: a) Develop test-plans, tests for SOC verification using UVM-SV and C-Based test flow . b) C rafting verification tests using both C and SystemVerilog (SV), including managing the communication and synchronization between these languages to ensure thorough feature verification. c) Should be able to debug the SoC test failures . d) Functional Coverage Model development and assertions development . e) Coverage(Code and Functional) analysis and closure . f ) Should be ready to collaborate with teams in different time zones . g ) Strong problem-solving and teamwork skills, and strong verbal and written communication skills Capable of quickly ramping up . h) Should be able to mentor manage juniors in the team Benefits: Competitive salary and performance-based bonuses. Comprehensive health benefits package. Work on cutting-edge technologies and impactful projects. Opportunities for professional development and career growth. Flexible work hours and remote work options available based on client s policy.

Accountable for driving collaborating mentoring coaching multiple medium (with a minimum of 8 members) to large sized teams (with a minimum of 21 members) by providing technical expertise in coding debugging and content development. Self manages to deliver the results with no guidance. Inspires team members; a lead who is looked upon by all the members for technical assistance Outcomes: Expert at bug monitoring tracking bug lifecycle triage and isolation Expert at coding modules libraries low level debugging code analysis and code review Perform component selection isolation RCA in the event of failure Adherence to the latest versions of feature document source code binaries w.r.t. testing development and debugging Adhere to project timelines and communicate effectively over emails and conversations Mentor teams in Automation/Debug to become more effective in their roles Keep thoroughly abreast of all the technologies especially the ones associated with automation debug and content development Develop overall team expertise on low-level coding debugging and content development Thorough analysis of requirements to provide measurable inputs in terms of ETA SLA TAT and milestones Train teams to analyse traces/core dump for defects reported internally or by customer to find the root cause Flexible and adaptable to the changing varied working environments shifts and extended working hours Conduct sync meetings regularly with stakeholders test content developers cross functional teams debug automation inventory teams for resolving issues and smooth functioning Solicit feedback regularly from project managers program managers technical architects PoC stakeholders and sponsors. Strive to implement changes to provide better customer satisfaction Provide strategic and tactical solutions for technical issues Constantly motivate and encourage team to be updated with all technical requirements to outperform their duties Facilitate actions and resolve issues to keep the team running; know whom to approach and when Thorough understanding of tools and applications used in the process. Suggest new tools and process enhancements Act as single point of contact for all technical solutions within the team Measures of Outcomes: Completion of all mandatory trainings Adherence to testing methodologies and compliance process Adherence to project schedule and timelines Isolation debugging RCA time taken as per project KPIs Implement at least one impactful process/innovation Outputs Expected: Requirement: Technical lead in debugging automation and content development hardware requirements and process changes for smart execution debug and development. Technical mentor with client management skills Ownership: Ability to undertake challenging domains tasks projects platforms demanding clients and complex processed project. Own multiple projects end to end as technical lead. Identify the project risks and mitigation plan with clients Quality: Ensure the quality of deliverables in-line with agreed standards guidelines fair and untampered. Analyse the test results and coordinate with the development teams for bug fixes. Define debug strategies/standards and BKMs. Document: Create documentation for ones own work requirement analysis project progress solutions designs best practices BKM and test reports Status Reporting: Report status of tasks assigned comply with project related reporting standards and processes. Publish reports periodically in a timely manner with utmost quality. Release: Adhere to release management process for test/debug execution milestones ETA and test reports Compliance: Adhere to lab trainings protocols coding standards test system setups test compliance and ESD strict delivery timelines Manage knowledge: Consume project related documents source code platforms features specifications and provide training to the team to upskill their capabilities. A go to person who know what to find where and whom to contact for assistance or technical guidance. Train team members regularly on new features best practices BKMs and processes. Skill Examples: Expert at code walkthrough and author of modules libraries Provide technical input to project management team Ability to troubleshoot boards/system and evaluate test results against system specifications Expert at rework/HW for automation environment Plans develops and implements best processes teams trainings Coordinates communication between technical architects and team Results drive self starter who anticipates initiates and implements solutions Create methods to leverage cross functional debug automation RD ability/capability Able to work in a team environment Good written and verbal communication abilities Excellent aptitude analytical and problem-solving skills Proactively ask for and offer help The organizational mechanism to share coding debug content learnings across teams Ability to work closely and independently with the client performing tasks per expectations Aid in project planning with respect to cost hardware software time and people Understand the criticality of the deliverables and perform accordingly Ability to handle multiple concurrent activities and projects Ability to work along with team distributed across locations Strong sense of ownership for assigned projects Knowledge Examples: Expertise in Hardware Engineering with strong knowledge of C C++ C# Python and relevant languages In-depth knowledge of Automation Programming or debugging techniques and methodologies Proposes multiple Hardware designs for Automation purpose Knowledge in microcontroller/processors 8/16/32 DSP/SoC based hardware architectures Knowledge in protocols interfaces I2C SPI UART USB Display PCIe Type-C Wi-Fi BT NVMe LPC TBT Capability with debugging tools like Function Generator Protocol analyser Oscilloscope Putty Tera term and Emulators Knowledge in hardware and product development lifecycles Knowledge in Agile methods for development debug testing implementation and execution Knowledge in electronic testing methodology and standards Experience with Source Code Management (SCM) tools like GIT Must be proficient with MS Office and Visio Expert at using ITP and Lauterbach Understanding on automation framework or system debug lifecycle JD:- Proven track record Experience with C/C++ in developing Embedded FW scripting automation using Python Proven ability to work as part of a global team in multiple geographies B.Tech. in Computer Science or Software / Computer / Electrical Engineering Requires 8-10 years of experience in RT / embedded systems architecture Multi-disciplinary experience, including Firmware, HW, and ASIC design Experience in using debug tools (JTAG, UART IEEE1500)

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes: Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: Quality -verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Number of new projects handled Outputs Expected: Quality of the deliverables: Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed Timely delivery: Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery Team Work: Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available Innovation Creativity: Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion training forum Skill Examples: Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB / AXI / PCIe / USB / Ethernet / SPI / I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks PR STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills Good analytical reasoning and problem-solving skills with attention to details Able to deliver the tasks on-time per quality guidelines and GANTT in every instance. Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project Knowledge Examples: Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of - RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill GCAD support engineer Job Requirements: Bachelor s degree in electronics or equivalent practical experience. 5+ years of experience in Physical designing, which includes low power designs, clock/voltage domain crossing, placement , CTS , routing . Experience with SOC cycles in ASIC designs Having some exposure to PPA improvement activities in PD. Experience in correlation activities like timing, DRC and congestion at different stages of Physical Design implementation. Expert in FC ( ICC2) Very good debugging skills for PD flow related issue Expertise with tcl, perl and python. Responsible to engage with PD team for Execution issues and follow-up to closure Candidate will be responsible in developing methodology solutions/convergence for new architectural features, Power, Performance Area improvements

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes: Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: Quality -verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Number of new projects handled Outputs Expected: Quality of the deliverables: Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed Timely delivery: Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery Team Work: Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available Innovation Creativity: Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion training forum Skill Examples: Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB / AXI / PCIe / USB / Ethernet / SPI / I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks PR STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills Good analytical reasoning and problem-solving skills with attention to details Able to deliver the tasks on-time per quality guidelines and GANTT in every instance. Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project Knowledge Examples: Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of - RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill Experience: 5- 10 Years Desired Skills and Experience: Engineers is expected to be very good in Basic Fundamentals of C-MOS technology Expected to have a very good understanding of the PD Flow for flat and hierarchal designs Able to handle RTL/Netlist to GDSII independently at block level/SS/SoC and should have done multiple tape outs with low power implementation (Experience on floor planning, Partitioning, integration at Subsystem/Chip will be add advantage) Should have hands-on experience of working on Lower technology nodes like 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm Exposure in DMSA flow for ECO generation and implementation. Good knowledge of VLSI process and scripting in TCL, perl .

Job description Essential Skills : Strong working knowledge on embedded C Hands on experience in complete V cycle development Development experience in micro-controller drivers, e.g. ADC, MCU, PWM, CAN, etc. Good at understanding of micro-controller CPU manuals / data sheets Good debugging skills Good working experience in Coding guidelines and other quality management frameworks and tools Good communication skills Preferred Skills: Various tools usage: LDRA, Tessy, Polyspace, etc. Working experience in Agile Technically guide the team Job Responsibilities: Develop and maintain MCAL drivers for latest micro controllers Capture and Analyse requirements Develop the Design Implement the Code Perform various testing Handle end to end development in Agile methodology Experience 5-10 years Bangalore

Job description Job Overview: We are looking for a skilled Embedded Software Engineer with strong proficiency in C programming, hands-on experience with microcontrollers and microprocessors, and understanding of ARM architecture. The candidate should also be proficient in communication protocols such as CAN, I2C, UART, and SPI. Candidate should have Knowledge of Bootloader development and Unified Diagnostic Services (UDS). A solid understanding of microcontroller peripherals is also essential. Knowledge of MQTT and FTP is an added advantage. Key Responsibilities: Design, develop, test, and maintain embedded software for various embedded systems. Write efficient, reliable, and maintainable code in C. Work on microcontroller and microprocessor-based embedded systems, ensuring optimal performance. Develop software for ARM architecture based embedded systems. Implement and troubleshoot communication protocols including CAN, I2C, UART, and SPI. Develop and maintain Bootloaders to ensure secure firmware updates. Work with UDS (Unified Diagnostic Services) for implementing diagnostic services and communication in automotive and embedded systems. Integrate and manage Microcontroller peripherals such as timers, ADCs, PWM, GPIOs, and other sensor interfaces. Collaborate with hardware engineers to integrate embedded software, testing and validation. Debug and test embedded systems, ensuring smooth interaction between software and hardware. Work with protocols like MQTT and FTP (optional) for data exchange and system integration. Experience: Minimum of 2-3 years of hands-on experience in embedded software development after Bachelor s degree in Electronics, Electrical Engineering, or a related field. Extensive experience with microcontroller peripherals and their integration in embedded systems. Experience debugging and testing embedded systems in real-world applications. Experience 2-3 years Bangalore

Job description Position Overview: We are looking for an experienced and dedicated Technical Lead to join our team. As a Technical Lead, you will oversee the technical direction, architectural design, and end-to-end development of projects. You will work closely with engineering teams, product managers, and stakeholders to ensure technical excellence, guide the team through challenges, and drive successful project delivery. Requirements: 1. Experience in AUTOSAR R4.x or later BSW (CAN, Diag.), RTE, OS, MCAL configuration, integration and Testing 2. Good debugging, Analytical and Problem-solving skills 3. Good knowledge in communication protocols like: CAN / LIN / Flexray / Ethernet 4. Good experience in using AUTOSAR configuration and generation tools like: Vector Davinci /EB TresOs etc. 5. Familiarity with project change and configuration management software, such as Jira, SVN, Clear Case, Clear Quest, PVCS or Change Synergy 6. Experience with Doors or equivalent requirements management software 7. Strong written and communication skills 8. Flexible to adapt for project dynamics, highly proactive and quick learner 9. Ability to work effectively in a collaborative team environment 10. Good embedded C programming experience 11. Good understanding on the embedded software build and test process 12. Good understanding of microcontrollers 13. Good experience in using Vector CANoe, CANanalyzer. Experience 8-12 years Bangalore

Job description PCB Hyderabad 4+years Candidate should have 4-5 years of experience in HW debugging Should have hands on experience in Vivado Tool Should have knowledge on PCB guidelines understanding. Need to work on Datasheet and other documents, should have good communication skill. Knowledge on different interfaces like I2C, SPI, Ethernet, CanFd, MIPI and IO interfaces etc. Experience 4+ years Hyderabad

Job description Harness Engineer 5 year Bachelor / Master s in Electrical engineering/Mechanical Engineering Minimum 5 years in Creo Cabling designing of Cabling systems. Understanding of product development process knowledge of all design phases from concept to implementation. Hands on experience in Low Voltage (LV) Panels and LV cables. Hands on experience on Windchill PDM link, CREO view or equivalent. Exposure to Electrical documentations like panel layout, electrical diagrams etc. Experience in working with Bill of Materials (BoM). ECM (Engineering Change Management) Experience with system integration/implementation (electrical/mechanical) Competencies Should be creative, result-oriented and have a good sense of responsibility. Should be aware of impact of technical decisions throughout the product lifetime. Good commercial/business understanding is desired. Should have good organizational and communication skills and you will be required to work within an international and multi-disciplinary team. Highly motivated and can work separately. Should have good English skills (speaking and writing) Experience 5 years Chennai

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities Skills What Will You Get to Do Do you have a passion for invention and self-challengeThis position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. What you re going to be exposed to and learn: The ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and training in the following areas: Chance to learn FPGA and it s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Validate and characterize various IPs from silicon arrival to release to production. Develop validation and characterization plans for certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc. Serve as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release. Supporting customer issues as required to resolve issues found after product release You Have 2+ years of experience Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation Knowledge in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe / Ethernet / SDI / CoaXpress / JESD204 , MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc. Knowledge in high speed board design and signal integrity evaluation/debug. Knowledge in Verilog/VHDL and design implementation using FPGA development tools. Knowledge in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R. Exposure on bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers. Exposure on FPGA(emulation/prototyping etc) Strong written and verbal communication skills to work with cross-functional team Self-motivated and proactive with critical thinking. Good problem solving and debugging skills. Who Are We At Lattice, we are good at collaboration and problem solving. We re also good at having a bit of fun. We develop technologies that we monetize through differentiated programmable logic semiconductor products, system solutions, design services and licenses. We are the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships and commitment to world-class support enable our customers to create a smart, secure, and connected world. Join Team Lattice and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what s next.

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded software, and system architects to ensure seamless integration. Debug FPGA designs using industry-standard tools and methodologies . Technical Skills Required: Strong understanding of RTL design (Verilog/VHDL) and FPGA implementation. Experience with FPGA tools such as Vivado, Quartus, Synplify, ModelSim, and QuestaSim . Hands-on experience with at least one of the following high-speed interfaces : PCIe, SATA, USB, DisplayPort, JESD204B, SRIO MII/RMII/GMII/RGMII/SGMII/XAUI/RXAUI DDR/LPDDR/DDR2/DDR3, QDR memories Knowledge of FPGA debugging techniques, timing closure, and constraint handling . Preferred Skills: Experience in FPGA-based hardware design and testing . Exposure to SoC architectures and system-level integration . GFPGA Design and Verification Engineer ) and power integrity (PI) analysis .G

Hardware Design Good Experience in High Speed Hardware Design. 1.relevant embedded hardware design 2. Proficiency in 8 bit, 16 bit and 32 bit microcontroller based designs 3. Proficiency in communication protocols like SPI, I2C, CAN, UART, USB, ethernet etc. 4. Experience in low power and low voltage, Power supply designs 5. Proficiency in schematics preparation in any of EDA tools is must. 6. Experience in hardware testing and validation is required 7. Experience in solving EMI/EMC problems is required 8. Knowledge about electronics product regulatory standards is required 9. Ability to guide PCB designer on layout and routing 10. Experience in board bring up, prototyping skills etc are required. 11. Knowledge in hardware Design work flow is required 12. Knowledge in configuration management tool is a good to have 13. Proficiency in high speed digital signal integrity analysis is an advantage

About The Role : Linux Kernel and Device Drivers, 6 to 10 years of hands on experience Role and Responsibilities 1. Responsible for the Linux Kernel and platform software, BSPs, Drivers (Yocto, Ubuntu, RedHat, CentOS), hypervisors, Boot Loaders, Diagnostics deliverable to the customer 2. Responsible for key Linux domains:Networking, GPU/Graphics, Multimedia. Experience and Skills 1. Should have prior experience in leading a team for Linux or Board Support Package delivery for ARM-Cortex or Intel x86 based SoC architectures and evaluation boards 2. Expert in ARM Cortex architecture or Intel x86 architecture based SoC architectures with a proven experience in Uboot based bootloader and Linux kernel and device drivers development and integration 3. Should have proven experience in technically leading mid-size team of 10-15 members 4. Should have experience in leading multi-disciplinary teams working on bootloaders, kernel development, device drivers integration, validation and verification and Linux OS bring-up 5. Prior hands-on experience in developing complex device drivers like PCIe Gen 4/5, USB 2.0, USB 3.0, Ethernet, SD and eMMC is an added advantage 6. Prior hands-on experience in kernel and device drivers debugging using gcc and gdb toolchain is preferred 8. Familiarity with GIT version control tool for software versioning and release packaging is required Do - Strategy Development and Deployment - Support development of overall practice charter for the organization - Achieve talent capability improvements by creating and deploying annual plan based on business strategy, requirement analysis and emerging business realities - Determine optimal structure and roles in the team for increased efficiency and effectiveness - Program / Intervention Design and Development - Address specific practice related challenges by working with business leaders to understand the problem, designing and deploying specific programs, processes or interventions. - Drive contextualization as per unit requirements, in programs deployed - Direct future capability building within the practice by developing new programs in consultation with business leaders, academia and external parties - Increase effectiveness of existing programs, policies or processes by commissioning and overseeing program redesign and refresh - Enhance the team design and delivery capabilities by devising and implementing frameworks for program effectiveness measurement - Team Management and Development - Provide overall direction and guidance to the team for program design and delivery - Complete all people processes for the team such as performance Nxt, WLQ etc. as applicable - Build team capability by reviewing team performance and recommending learning / development intervention in consultation with the concerned teams - Support & motivate the team by - - Coaching team members to build expertise and skill within the function - Driving focus in the team by aligning them with annual plans and performance goals - Encouraging team to undertake self-development and capability building.

Board bring-up, Soldering, Schematic reading, SMD Part exp., Repair, Troubleshooting. Required Candidate profile B.Tech/M.Tech in Electronics/Computer Engg. Experience with Board bring up & embedded systems.

Board bring-up, Soldering, Schematic reading, SMD Part exp., Repair, Troubleshooting. Required Candidate profile B.Tech/M.Tech in Electronics/Computer Engg. Experience with Board bring up & embedded systems.

Design Verification Engineer In-House ODC Project We are looking for an experienced Design Verification Engineer to be part of our in-house ODC project . The ideal candidate will be an individual contributor with expertise in SoC, Subsystem, or IP verification using high-speed serial protocols and advanced protocols . The candidate should have a strong command of SystemVerilog (SV) and UVM , including writing test cases, sequences, OOPs concepts, and UPF implementation . The role requires hands-on experience in scratch-level work , ensuring verification coverage from the ground up. Experience: 4 to 20+ years Location: Bangalore, Chennai, Pune Notice Period: Immediate to 30 days If you're ready to take on challenging verification tasks and contribute to cutting-edge projects, apply now!

Experience: Minimum of 6+ years in software development, focusing on embedded systems. Hands on experience with Linux, Yocto BSP, ARM, and x86 architectures. Strong background in systemlevel programming for Linux and developing device drivers. Skills: Programming Languages: Proficiency in assembly language, C, C++. Embedded Systems Expertise: Development of device drivers for hardware interfaces such as USB, ATA, Video, Audio, Ethernet, CAN, NAND flash, NOR flash, DDR3/4, SDRAM, HDMI, PCI Express, SPI, and I2C. Knowledge of wireless technologies like 802.11, WiFi, Bluetooth, GPS, and cellular. Tools Methodologies: Familiarity with Agile/Scrum development methodologies. Experience with tools like spectrum analyzers, oscilloscopes, and JTAG debuggers. Processor Platforms: Extensive experience with ARM Power PC and x86 processor cores. Operating Systems: Proficiency in developing software for Linux with Yocto BSP platforms, Experience with Android is optional. ","KeyResponsibilities":" Responsibilities: Lead the design and development of software for 8, 16, 32, and 64bit processor platforms. Develop and optimize software in assembly language, C, C++ for

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities Skills Lattice Semiconductor is seeking a Principal to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time Principal Engr position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will lead the design and development of complex components of FPGA, ensuring they meet performance, power, and area targets The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with architecture team to define micro architect and design spec Serve as a technical expert in SoC design, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student. Accountabilities: Serve as a key contributor to FPGA design efforts. Drive logic design of key FPGA system full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality throughout project development conducting regular reviews and audits Work with cross functional team including program management, package design, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up-to-date with the latest industry trends and technologies Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 15+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Expertise in working with ARM processor, AXI, AMBA bus, ENET, PCIE, USB, safety and/or security protocols, debug architecture. Experience in leading the project through out design cycle and working with cross organization Familiarity with FPGA designs, use-cases, and design considerations is a plus. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Design and develop cycle approximate/Loosly timed C++/SystemC models for Cadence s IPs like PCIe controller, etc for use in early SW development ,architectural exploration and performance analysis at different levels subsystem and SoC level. Design and develop protocol specific functional models for various Cadence s interface IPs like PCIe , UCIe , CXL , USB , Ethernet , UFS , DP , etc Interact with IP designers and architects to understand various IP design/implementation specification and behavior Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks Documentation of design specifications, implementation details, FAQ s, application notes, etc For additional details and the most recent updates, hit Apply for job About Navigation Copyright 2013 2025 SMG | | Manage consent