28 Ucie Jobs - Page 2

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

KEY EXPERTISE : - Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. - Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. - Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. - Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. - Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. - Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. - Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). - Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. - Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. - Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. - Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. - Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. - Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. - Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. - Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. - Good Team Player : Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. - Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .