Strategic / Leadership Role Advanced Micro Devices, Inc

20.0 - 24.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: You will be working as a Fellow Silicon Design Engineer at AMD to develop world-class Server products. Your main responsibility will be to define and drive PPA uplift methodologies, develop power optimization methodology for Physical Design Implementation, define PVT corners and frequency targets for next-generation Servers, and have a deep knowledge of micro-architecture, power optimization methodologies, and timing closure. You are expected to have very strong problem-solving skills, broad experience in methodology, and a self-motivated work ethic to provide a cohesive technical vision for PPA improvement methodology. Key Responsibilities: - Define and drive PPA uplift metho...

Posted 1 month ago

AI Match Score

Apply

STA/Timing Methodology Sr Staff Engineer Qualcomm

5.0 - 10.0 years

5 - 10 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Key requirements: Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. 10 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Strong understanding of advanced STA concepts and challenges in advanced nodes Proficiency scripting languages (TCL, Perl, Python). Strong background in PNR and Extraction domain. Experience of constraints development tool (like spyglass) will be added advantage. Leadership qualities to lead (technically) and manage the STA CAD team Qualification: BE/BTech + 12 years of experience, or ME/MTech + 10 years of experience Minimum Qualifications: Bachelor's deg...

Posted 5 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.