8 Timing Ecos Jobs

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for p...

JD - Domain :: STA (Static Timing Analysis) Work Experience :: 3 8 years Location :: Noida Tool Expertise :: PrimeTime & PT-ECO Technical Expertise :: Block level Timing Constraints generation, enablement & analysis across Functional & DFT modes ; Clocking & Data flow understanding ; Good in interaction with Design (FE) & DFT teams for better understanding ; Well versed in reviewing check timing and Constraints QoR checks + Constraints Validation understanding ; Able to interact with Implementation team counterparts for block timing closure ; CTS building understanding along with Clock Tree spec review/closure ; Timing ECOs & Final Timing last mile closure at block level ; Scripting like TCL...

As a Static Timing Analysis (STA) Engineer with 3-8 years of experience in Noida, your role will involve the following key responsibilities: - Generate, enable, and analyze block-level timing constraints across Functional and DFT modes. - Understand clocking and data flow within the design, and effectively communicate with Design (FE) and DFT teams for enhanced comprehension. - Review timing checks and Constraints Quality of Results (QoR) checks, and have a strong grasp of Constraints Validation. - Collaborate with Implementation team counterparts to achieve block timing closure. - Understand Clock Tree Synthesis (CTS) building and participate in Clock Tree specification review and closure. ...

As a Static Timing Analysis (STA) Engineer with 3-8 years of experience, you will be based in Noida and expected to have expertise in PrimeTime & PT-ECO tools. Your responsibilities will include: - Generating, enabling, and analyzing block-level timing constraints across Functional & DFT modes - Understanding clocking & data flow and effectively communicating with Design (FE) & DFT teams - Reviewing timing checks, Constraints QoR checks, and validating constraints - Collaborating with Implementation team for block timing closure - Understanding CTS building and reviewing/closing Clock Tree spec - Handling Timing ECOs and ensuring final timing closure at the block level - Proficiency in scrip...

block-level timing constraints ,functional and DFT modes,STA analysis and closure ,PrimeTime,PT-ECO ,QoR,constraints validation,Front-End Design,DFT teams,Clock Tree Synthesis,Timing ECOs,TCL, Unix shell scripting Contact-gagan@bestnanotech.in

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routability analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routablity analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes, ...

Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Knowledge on Power analysis and PT-PX flow Your Profile You are best equipped for this task if you hav...