888 Timing Closure Jobs - Page 26

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic ...

Synaptics is looking for a Principal Digital Engineer, WLAN MAC to join our dynamic and growing WPD organization. You will be responsible for MAC architecture / design / implementation in the Wi-Fi 6/7 for IoT market. You will provide technical expertise in the latest design methodologies. You will provide expertise in Wi-Fi domain. Your responsibility includes coordinating with multiple teams on specification for design, architecture, timing closure. This position reports to the Director, Silicon Engineering. Responsibilities & Competencies Job Duties Define WiFi MAC architecture from Standard Technically lead team on design, methodology Design optimization, enhancement to cater to the need...

We are looking for a highly skilled and experienced Sales Manager to join our team at Capital Placement Services. The ideal candidate will have 6-8 years of experience in sales management, preferably within the employment firm or recruitment services industry. Roles and Responsibility Develop and implement effective sales strategies to achieve business objectives. Lead and manage a team of sales professionals to meet targets. Build and maintain strong relationships with clients and stakeholders. Conduct market research and analyze trends to identify new business opportunities. Collaborate with cross-functional teams to drive growth and revenue. Monitor and report on sales performance metrics...

is a Gurgaon based Placement Consultancy that specializes in providing Placement Services, Manpower Recruitment, HR Consultancy, Placement Consultancy and Staffing Solutions. We are looking for Our Esteemed Client in Gurgaon Industry HR Recruitment Administration IR Training & Development Operations Qualification Other Bachelor Degree Key Skills HR HR Analyst HR Assistant HR Associate HR Consultant HR Coordinator HR Head HR Incharge HR Generalist

Job Title: FPGA Architect Location: Gurgoan, HR Experience: 10+ Years Job Summary: As FPGA Architect, you will lead the design development effort on a variety of projects in a highly collaborative, fast-paced environment. In this role, you will be responsible for the definition and development of complex FPGA designs for our Test products. You will work closely with RD Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US Europe. Qualifications ...

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effec...

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

Physical Design Engineer Lead - InSemi Tech Physical Design Engineer Lead Bangalore | 8 Years Key Responsibilities Technologies Below 14nm 10nm,7nm,latest one ..3nm Block level floor planning and IR drop analysis Block level timing closure with sign off STA Proficient in physical Design methodology which include logic synthesis, placement ,clock tree synthesis, routing

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation . Must have hands-on experience on Synopsys/Cadence tools. Should have experience on PD Methodologies and submicron technology of 28nm and lower technology nodes.

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-7 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise a...

Urgent Opening for Sr Engineer- Physical Design Posted On 06th Oct 2017 11:52 AM Location Bangalore Role / Position Sr Engineer- Physical Design Experience (required) 3- 9 yrs Description : Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation; Expertise in ...

Urgent Opening for Physical Design Sr Engineer / MTS / SMTS Posted On 27th Jun 2017 01:05 PM Location Bangalore / Hyderabad Role / Position Physical Design Sr Engineer Experience (required) 2-7 Years Description Designation :Physical Design Sr Engineer / MTS / SMTS Experience: 2 to 7 Years Location :Bangalore /Hyderabad : Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GD...

Skills Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR Subsystem timing closure and Subsystem physical verification Experience 10-15years Job Location Bangalore, Hyderabad, Noida, Coimbatore Job Type Full Time

Skills SOC Physical Design Experience 3 to 15 years Job Location Bangalore, Hyderabad, Noida, and Coimbatore. Job Description: Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool ...

Job Details: Skill: SAP BODS Location: - PAN INDIA Notice Period: Immediate Joiners Employee type : C2H/FT Job Description: 1.Open to Hire/Work from any city 2.People with Total Exp of 6 + and mandatory 4 + exp in BODS will be considered 3.Notice : 2/3 weeks will be considered not more than that 4.Knowledge & Exp on SQL and PL/SQL along with BODS is required. Should have experience in Data Migration. 5.Open to Freelancers without any complications in the future (minimum 30 hrs support). 6.Work timings : 1pm to 10pm.

5 to 7 years experience in both BW and Native HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical conceptswith focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions Shift timings : 2 PM to 11 PM

The ASIC Back-End Head is responsible for leading the physical design and implementation of Application-Specific Integrated Circuits (ASICs), ensuring optimal performance, power efficiency, and manufacturability. Key Responsibilities Strategic LeadershipDefine and execute the ASIC back-end design roadmap. RTL to GDSII Flow ManagementOversee synthesis, floorplanning, placement, routing, timing closure, and sign-off. Physical Design OptimizationEnsure Power, Performance, and Area (PPA) targets are met. EDA Tool ExpertiseWork with Synopsys, Cadence, Mentor Graphics tools for ASIC implementation. Cross-functional CollaborationCoordinate with design, verification, DFT, and packaging teams. Tape-O...

Shrimad Rajchandra Mission Dharampur is looking for Senior Placement Officer to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews a...

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3....

STA flow setup, convergence, reviews Timing constraint development, analysis, validation and debug Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner STA flow optimization Work ondesign automation using TCL/Perl/Python Position Requirements: BTech/MTech degree in Electrical/Electronics with 2-10 years of experience Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below). Ability to develop complex timing constraints by working with designers. Should have experience in IP/subsystem/full-chip timing constraints Knowledge of timing commands and constructs supported across synthesis, STA a...

Lead development efforts for AMS design collaterals generation fortop level integration, ensuring optimized performance Job Description In your new role you will: Lead development efforts for AMS design collaterals generation for top level integration, ensuring optimized performance. Enforce consistency of all required views for AMS macro integration. Ensure quality of digital design deliverables to RTL2GDS counter parts by running preliminary RTL synthesis and timing checks. Identify and apply methodologies to allow optimal timing closure of complex AMS IP (ADCs, clocking) in the context of digital-on-top integration. Collaborate with cross-functional teams, including digital design,AMS des...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collabora...

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Qualcomm is looking for an experienced Chipset Power System Engineer who is passionate in solving power challenges and develop innovative solutions for optimizing power for next generation Snapdragon chipsets of various platforms in applicator processor, modem, automotive, AR/XR, compute and machine learning. The engineer is expected to work with cross-functional engineering teams to model SOC/chipset power and come up with innovative solutions to optimize hardware and software to enhance SOC and chipset and achieve world-class chipset low power consumption. In this position, the engineer will support the e...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...