600 Timing Closure Jobs - Page 24

Job Purpose "This position is open with Bajaj Finance ltd." To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems and submit BRD 9.Interacting with field teams to identify the exact issues Required Qualifications and Experience ducational Qualifications a)Graduate or equivalent b)1+ years of experience Finance industry support of system c)Well versed in MS Office d)Agile ability on the work timings

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 3-5 Years.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). 2. Experience on hierarchical designs and/or Low Power implementation is an advantage. 3. Experience on Synthesis, interfacing with RTL and implementation 4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques. 5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements). 6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, timing fix implementation, timing ECO generation. Knowledgeable in physical design flow, logic. Experience with timing fixes (slack, electrical, noise). Preferred technical and professional experience Require programming skills with any language PYTHON, PERL , and/or TCL .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 1-3 Years.

Must Have Skills Floor Planning/Innovus/Fusion Compiler Good to have Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Mandatory Skills: VLSI Physical Place and Route.Location- Bangalore/ Pune/ Hyderabad/ Kochi

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Bangalore Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Turn your weekends into an earning opportunity!

Job Description: We are looking for an experienced Physical Design Engineer with strong expertise in EMIR analysis and end-to-end RTL to GDSII flow. The ideal candidate should have hands-on experience in physical design, power integrity, and timing closure at advanced process nodes. Key Responsibilities: Handle complete RTL to GDSII implementation Perform EMIR (Electro migration and IR drop) analysis and closure Conduct timing analysis , power planning , and floor planning Run and debug DRC , LVS , and STA reports Work on advanced technology nodes (e.g., 7nm, 5nm ) Collaborate with cross-functional teams (FE, DFT, verification, etc.) Automate flows using Python , TCL , or Perl Required Skills: Strong experience in Physical Design Hands-on expertise in EMIR tools and flow ( Highly Important ) Proficiency in EDA tools (Cadence Innovus, Synopsys ICC2, Prime Time, Mentor Calibre) Understanding of VLSI Design Principles Familiarity with low power design methodologies Good scripting skills in Python, TCL, Perl Excellent analytical, problem-solving, and communication skills

Expectations/ Requirements: l Key account Manager is principally responsible for Signing New Logos/ Merchants/Brands from Large Enterprise / Corporate Accounts. l The BDM achieves these goals by creating Funnel and Closure of accounts. Superpowers/ Skills that will help you succeed in this role: l Adaptability: Attitude of optimism and can-do orientation with ability to think creatively and navigate successfully past barriers and obstacles l Focus through the Noise: Ability to tune out distractions to focus work on priority goals and tasks l Persuasion: Ability to present concepts, ideas and proposals in a manner that is perceived positively by and clearly resonates with intended audiences and stakeholders, while encouraging action. l Professionalism: Ability to project a mature and professional attitude, demeanor and appearance as is appropriate to a given situation l Sense of Urgency: Ability to prioritize, plan and move decisively when necessary to meet timeframes to avoid timing crises.

You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 5+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

The analyst will produce high-quality written content that communicates complex market dynamics clearly. Support insights with compelling visuals such as charts and graphs. The candidate will engage regularly with clients through calls, meetings, conferences, and events delivering tailored insights, explaining methodologies, and articulating value propositions. Responsibilities The analyst will conduct power modelling for power markets to deliver short-term market forecasts in client-facing reports. Key considerations in modelling may include, but are not limited to: Capacity build-up. Thermal fuel switching. Temperature-adjusted power demand. Power market mechanisms and price settlement methods. Carbon emission policy, cost, price and new technologies. Power and renewables policies, market trends and key players. Requirements A university degree in economics, business, public policy, or a related field. Familiarity with broader commodity markets, especially in the energy sector. Excellent English communication skills (reading/writing/speaking). Experience building forecasts or models. Knowledge of electricity markets in South and Southeast Asia. Experience with integrated cross-commodity analysis. Strong team players who can work across geographies and time zones. Proven ability to write clearly, visualize data effectively, and present complex analysis in high-level engagements and public forums. Having experience from a similar role is a plus.

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.

Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. - Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. - Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. - Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance. - Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team s workflow. - Prepare and present detailed timing reports and technical documentation to stakeholders - Foster a culture of innovation, collaboration, and continuous improvement within the STA team. Qualifications - Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. - A minimum of 5 years of experience in Static Timing Analysis. - Proven t

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD s data fabric IP , working in close coordination with verification to ensure design quality. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data center application systems. Responsible for the inter IP integration issues resolution Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques, UPF included PREFERRED EXPERIENCE: 6 to 10 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Active knowledge of ASIC design quality flows Knowledge of cache coherency and /or fabric /NOC design is a plus Low power analysis and design Version control systems such as Perforce, Git ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD s data fabric IP , working in close coordination with verification to ensure design quality. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data center application systems. Responsible for the inter IP integration issues resolution Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques, UPF included PREFERRED EXPERIENCE: 6 to 10 years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Active knowledge of ASIC design quality flows Knowledge of cache coherency and /or fabric /NOC design is a plus Low power analysis and design Version control systems such as Perforce, Git ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2

Job Details: Job Description: As a RTL Design Hardware Engineer within the Software Performance and Integration group, you are expected to work on the RTL underpinning Altera's System-on-Chip integration tool, Platform Designer, FPGA Debug Environment Tools such as SignalTap and System Console. The goal of this team is to implement powerful embedded hardware systems using a straightforward flow from design creation through debugging and performance optimization. The team is responsible for development of RTL for various soft IPs, including an on-chip Memory Mapped Interconnect ( AXI/APB/AHB/Avalon) , streaming protocols IPs ( AXI / Avalon ), debug IP such as signaltap, ISSP, ISMCE, bridge and adapter IPs and supporting a full stack of tools which assemble these IPs in interesting and dynamic ways. As a Hardware Engineer in this position, you will need to be excellent at digital design with expertise in VHDL/Verilog/System Verilog with responsibilities as listed (but not limited to) below: Lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs Coming up with newer versions of on-chip transfer protocols aimed for high speed for our latest FPGA s using hyperflex architectures Developing new Interconnect topologies to maximize data transfer throughput over long distances Extending support for industry standard Memory Mapped and Streaming protocols Developing robust IP and networks which customers use in mission critical debug environments Work with RTL Design Verification team to review and supervise the verification of the IPs developed The RTL design engineer will have a direct influence on our customers and the adoption of our products, with tasks including the following: Work closely with developers across software, IP and embedded engineering to ensure we develop design flows that meet our customers' needs Guide IP release content, and serve as a liaison with the support, field, marketing, and product planning organizations Research, define, and validate key customer use cases Create reference RTL designs and regressions tests Use Altera FPGA design tools like our customers to identify usability and productivity problems or missing features Qualifications: Qualifications : BS/MS/PhD degree in Electrical/Computer/Software Engineering or equivalent and 10+ years of relevant industry experience Strong understanding and knowledge of digital design/Timing Closure concepts/Fundamentals of Verification/Hardware Debug Strong experience in Verilog and System Verilog Understanding of Computer Architecture/ARM Based Bus Protocols Understanding of other communication protocols will be plus Knowledge of Quartus or Vivado tool flow is a plus Tcl, Perl, and/or Python scripting skills Dedication to customer experience and usability Strong written and oral communication skills Ability to influence across organization boundaries Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations:

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. Role Join our close-knit physical design team where you'll excel in synthesizing, placing, routing and integrating high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture. Minimum Skills & Qualifications 10+ years of physical design, integration & physical verification experience. Strong knowledge of block level and full-chip physical verification methodology. Experience with the complete physical design flow. Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. Expert with IR/EM analysis and resolution Good understanding of full chip floor planning and integration. Strong experience in full chip timing closure Demonstrated ability to work with RTL teams to optimize for physical design Ability to independently debug and resolve physical verification Issues BS or MS in Electrical Engineering Preferred Skills: Knowledge of Synopsys tool suite is a plus. Good scripting skills with languages like Tcl and Python. Ability to make flow enhancements. Why Join Cerebras People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras: Build a breakthrough AI platform beyond the constraints of the GPU. Publish and open source their cutting-edge AI research. Work on one of the fastest AI supercomputers in the world. Enjoy job stability with startup vitality. Our simple, non-corporate work culture that respects individual beliefs. .

We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform f loorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages. Drive physical verification (DRC, LVS, antenna checks) and resolve violations. Perform congestion analysis and optimization for flat SoC designs. Work with methodology teams to improve PNR flow and scalability. Mentor junior engineers on PNR best practices and advanced Cadence Innovus features. Qualifications Must-Have: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10-12 years of hands-on physical design and PNR experience. Proven ability to handle flat SoC designs in Cadence flow Strong knowledge of floorplanning, CTS, routing, optimization, and sign-off closure. Solid understanding of STA, SDC creation, and ECO flows for physical implementation. Prior technical leadership or mentoring experience. Nice-to-Have: Automotive semiconductor experience Low-power implementation (UPF/CPF). Experience with scripting ( Tcl, Perl, Python ) for automation.

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success. Key Responsibilities Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out. Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows. Perform setup, hold, recovery, and removal analysis using industry-standard STA tools. Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams. Work closely with clock, power, and signal integrity engineers to address timing and noise-related issues. Lead STA reviews with design and physical implementation teams, ensuring issues are tracked and resolved. Collaborate with methodology teams to enhance STA flows and timing sign-off quality. Contribute to methodology improvements for STA and PNR flows. Mentor and guide junior engineers in STA and timing-driven PNR techniques. Qualifications Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10-12 years of hands-on experience in STA for large, complex ASIC/SoC designs. Proven PNR experience to handle flat SoC designs in Cadence flow. Solid understanding of multi-mode, multi-corner (MMMC) timing analysis. Proficiency in timing constraints writing (SDC), clock domain crossing (CDC) considerations, and asynchronous interface analysis. Experience with ECO timing closure and post-route sign-off. Prior experience in team leadership or technical mentoring . Nice-to-Have: Familiarity with scripting languages ( Tcl, Perl, Python ) for flow automation. Exposure to low-power design techniques (UPF/CPF). Knowledge of signal integrity, EM/IR drop impacts on timing. Experience in the automotive industry is a plus Send Us A Message Recaptcha requires verification. I'm not a robot US Office 5005 W Royal Ln Suite 224, Irving, TX 75063 India Office Plot No 133, Sri Hari Nilayam, Vaishali Nagar, Madinaguda, Hyderabad - 500049

Position: Synthesis + STA Engineer (SI80FF RM 3488) Responsibilities & Required Experience: Strong understanding of timing closure for multi-clock, high-frequency timing, congestion, crosstalk, and area-sensitive designs. Collaborate with RTL designers for constraint development and cleanup. Proficient in Synopsys/Cadence tools with hands-on experience in advance features of Design compiler and PrimeTime SI. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe Provide technical leadership to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm). Good scripting, communication and debugging skills. Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 8+ years Notice period: 0-15 days

Role Overview We are expanding our team in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems You will collaborate across analog and digital teams to deliver high-performance, reliable solutions for next-generation automotive networks Required Skills + BS/MS/B Tech/M Tech in Electrical Engineering or related field + 8+ years of experience in digital design for communication systems + Expertise in Verilog/SystemVerilog, Ethernet or similar protocols, and PHY layer design + Strong understanding of PLLs, clocking schemes, and timing closure + Experience with analog IP integration and cross-domain collaboration + Familiarity with automotive standards and reliability requirements Preferred Skills + Knowledge of automotive Ethernet (100BASE-T1, 1000BASE-T1) or similar high-speed serial standards + Experience with IP, subsystem-level design and integration + Proficiency in scripting languages (Python, TCL) and simulation tools + Strong documentation and communication skills Why Join UsJoin us in shaping the future of the connected car driving innovation in vehicle connectivity, safety, and automation through cutting-edge automotive networking technologies and high-performance communication systems Collaborate with a global team to redefine mobility and enable the next generation of intelligent vehicles \#LI-RG1 onsemi*(Nasdaq: ON) is driving disruptive innovations to help build a better future With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world s most complex challenges and leads the way in creating a safer, cleaner, and smarter world More details about our company benefits can be found here: https://www onsemi com/careers/career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work