880 Timing Closure Jobs - Page 17

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

Job Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate constraints from multiple IPs for hierarchical STA. Tool Usage & Flow Integration Use STA tools like Synopsys PrimeTime, Cadence Tempus , or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, an...

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to ma...

Role: Design Analysis Engineer (FPGA/Vivado) [M.Tech Mandatory] What they do: Analyze design issues in Vivado implementation flow. Apply and debug timing constraints to ensure design closure. Propose/design corrections to fix issues. Use scripting (Shell/Python/TCL) to automate and improve analysis. (RTL/Verilog knowledge is optional, not mandatory.) Mandatory Skills: Strong in Timing Constraints (STA concepts) Hands-on with Vivado tool flow Shell/Python/TCL scripting for automation Good to have: Quartus exposure Basic RTL/Verilog understanding In short: This is not an RTL coding role. Its a timing + Vivado design analysis role with scripting. Feel free to share the resume if you feel its a ...

Role & responsibilities Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on the latest technology nodes (14nm or lesser). Must have experience in Static timing analysis Must have experience in Physical verification and appropriate fixes Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Location: Bangalore/Kochi/Chennai

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, sc...

B.E / B.Tech in ECE / EEE 3 to 7 years Brief JD: Development of FPGA logic for signal processing, control logic, or high-speed interfaces. Detailed JD: Job Description: Design and simulate FPGA logic using VHDL / Verilog. Develop and integrate IP cores for VPX/VME boards. Perform timing analysis, floorplanning, and optimization. Interface with embedded software and hardware teams. Support lab testing and verification on hardware platforms. Professional Skills / Technical Knowledge: Experience with Xilinx (Vivado), Intel (Quartus), or Lattice toolchains. Strong understanding of timing closure, constraints, and protocols (PCIe, Ethernet). Hands-on with test benches, simulation tools. Defense a...

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Leve...

You have 7 to 10 years of experience and the job is located in Bangalore with the requirement to work from the office. As an experienced engineer joining our team, your primary skill requirements will include exceptional digital fundamentals. You should have hands-on experience in system design with FPGA devices using relevant FPGA EDA tools. Additionally, you are expected to have experience in designing and implementing FPGA-based solutions using Microchip, Xilinx, or Altera FPGAs. Your responsibilities will also involve writing high-quality code in Verilog/System Verilog, VHDL, and C for embedded processors, as well as maintaining existing code. Moreover, you will be responsible for develo...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundarie...

Your Role Implement and configure SAP Document and Reporting Compliance (DRC) in S/4HANA environments. Design scalable solutions for global e-invoicing and statutory reporting. Integrate SAP DRC with FI, SD, and MM modules for accurate compliance. Collaborate with technical teams for interface development and automation. Support legal change management and country-specific compliance updates. Your Profile 4-12 years of SAP functional consulting experience, including SAP DRC (ACR). Strong knowledge of global statutory reporting and e-invoicing frameworks. Hands-on experience with SAP DRC configuration across multiple countries. Proficient in S/4HANA and integration with core SAP modules. Exce...

Responsibilities As a creative Design Constraints Engineer, you will be part of the Front-End Design team, developing, validating , optimizing , and handing off constraints for complex SoCs, ensuring robust timing closure and seamless integration across the various stages of SOC design cycle. Your key responsibilities will include creating and maintaining Design constraints, validating them using industry standard STA tools and handing off to the Implementation teams. You will closely work with the Design team to capture the Design constraints. You will be validating these constraints using industry standard constraint validation tools like Time Vision and other equivalent tools. You will pa...

As a part of Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical implementation, Timing closure an...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated ...

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate shoul...

Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master...

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times I...

Job Role: * Collaborate with cross-functional team on timing closure. * Perform STA using TCL and MMMC tools. * Ensure compliance with industry standards during static timing analysis. Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is req...

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Role Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area / power / performance / convergence) , develop plans and deploy/support them Powe...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...