600 Timing Closure Jobs - Page 16

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

Physical Deisgn Lea LocationBangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experienceon Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: VLSI Physical Place and Route. Experience5-8 Years.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What we need to see: BE/BTECH/MTECH, or equivalent experience. 4+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fundamentals and experience in Synthesis and STA domains.. Write and implement block level and top-level timing constraints for Synthesis. Optimize designs for power, performance, and area, and meet design goals.. Knowledge on Power analysis and PT-PX flow.. Understanding of DFT flows, including scan insertion.. Write and evaluate Test/DFT mode timing constraints.. Thorough with Logic Equivalence Check debug capability.. Well known about UPF concepts and Low Power Checks at block and full chip level.. Defining and verification of STA constraint for Functional and Test/SCAN Modes.. Defining PVT’s corners required for covering all desired scenarios for a design. Knowledge on OCV/AOCV/POCV derates.. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.. VASTA timing closure based on chip IR drop.. Knowledge on signal SI analysis and PT-PX flow.. Contact:. swati.gupta@infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct ( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

PMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for a senior DFT Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define/implement the DFT Architecture and technically guide and lead the DFT execution team. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean tape-out and silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel well within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance .

15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs final tape-out timing closure skills across corners and modes Must work with RTL design team, PD team, and HMs team for overall timing closure for SoC

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus tools. Interested candidates can contact me at shubhanshi@incise.in

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 2 to 5 years of experience Company Description

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Roles and Responsibilities Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through recent successful SOC tape-outs Experience 5+ Years of experience Qualifications B.Tech/B.E/M.Tech/M.E

Roles and Responsibilities Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies Executed scan & MBIST insertion, ATPG and verification at full chip level Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts Generate, review and validate DFT constraints to achieve timing closure of high speed design Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved Understanding of Power Estimation/Management for DFT modes is preferred Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples Strong written and oral communication skills Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E

Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities 5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas: Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes MBIST architecture planning, repair architectures, insertion, verification Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team Timing GLS, debug of fails in simulations Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable Understanding of functional test cases, IO testing, testing of ARM processor cores Ability to lead a team across all aspects of DFT, interact with RTL, physical design teams for DFT implementation, anticipate risks, plan project timelines and milestones Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *