880 Timing Closure Jobs - Page 15

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engin...

General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with ...

General Summary: You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering...

This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top. Candidate will work on various stages of physical design implementation which includes floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks. Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques. Candidate should have good understanding ...

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond). Ownership of constraints development for functional/test modes at pre and post layout stage. Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces. Timing analysis and convergence of large hierarchical design across multiple modes and corners. Interact with RTL and DFT teams on timing feasibility and performance assessment. Work...

1. Deep Submicron Technology Experience: Hands-on experience with SYN/APR/Signoff and tapeout in deep submicron technology. 2. Familiarity with EDA Tools: Proficient in using EDA tools such as ICC, ICCII, and INNOVUS.3. ASIC Flow Knowledge: Well-versed in the ASIC design flow.4. Programming Skills: Proficient in Tcl, Perl, scripting, C, and C++ programming languages. 5. Strong Communication Skills: Excellent communication abilities. 6. Proactive and Responsible: Highly proactive, enthusiastic, and responsible. 7. Education and Experience: MS degree with at least 2 years of experience in the PnR field is preferred. 8. Large-Scale Design Experience: Experience handling designs with more than 2...

In this role, you will be leading all block/chip level physical design activities. This includes tasks such as generating floor plans, abstract views, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. Collaboration with the design team to address design challenges will be a key aspect of this position. You will also be assisting team members in debugging tool/design related issues and constantly seeking opportunities to enhance the RTL2GDS flow to improve power, performance, and area (PPA). Troubleshooting various design issues and applying proactive interventions will be part of your responsibilities. Your main responsibility will be overseeing all aspects of...

As a Senior Physical Design Engineer with Micron Technology, you will play a crucial role in the HBM Team based in Hyderabad, India. Your primary responsibility will be to design and develop complex Application-Specific Integrated Circuits (ASICs) catering to the requirements and specifications of High Bandwidth Memories (HBM). These memories are utilized in intensive applications like artificial intelligence and high-performance computing solutions, aiming to push the boundaries of technology and innovation. Your role involves designing IPs or Hierarchical blocks solutions for high-performance and low-power applications. You will collaborate closely with cross-functional teams to define pro...

At AMD, we are dedicated to transforming lives with our cutting-edge technology to make a positive impact on our industry, communities, and the world. Our goal is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. Central to our mission is the AMD culture, where we continuously strive for innovation to address the world's most pressing challenges. We are committed to achieving excellence in execution while upholding values of directness, humility, collaboration, and inclusivity of diverse perspectives. As a SOC Physical Design Director at AMD, you will play a ...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues2.Resolving BRE level issues3.Educating internal and field teams on issues due to training requirements4.Constant observations on the issues raised by the field team5.Raising regular IT request to resolve issues6.Constant communication between IT and Product teams to identify the changes7.Attending bi-weekly meetings with IT to find the bigger solution8.Find solutions to the repetitive problems and submit BRD9.Interacting with field teams to identif...

Job Purpose This position is open with Bajaj Finance ltd To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement Duties and Responsibilities Resolving SFDC functions related issues2 Resolving BRE level issues3 Educating internal and field teams on issues due to training requirements4 Constant observations on the issues raised by the field team5 Raising regular IT request to resolve issues6 Constant communication between IT and Product teams to identify the changes7 Attending bi-weekly meetings with IT to find the bigger solution8 Find solutions to the repetitive problems and submit BR...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling differen...

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etcYou are meticulous about Power, Performanc...

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etcYou are meticulous about Power, Performanc...

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, C...

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing ...

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Gr...

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Work with IP SOC teams across all our sites (GFX, Memory controller, Multimedia engines, IOs, PCIE ) to understand the features and create verification plans Will help scoping out the testbench architecture and the simulation configuration, test planning, coverage planning etc Will develop system config and initialization sequences to various system configurations at the SOC Will work with Graphics/IO IP team and verify some of the grap...

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who hasexcellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Working on static timing analysis setup and signoff of multi-corner multi-voltage designs. Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Areas of focus include Timing analysis and verification, extraction and noise glitch analysis Engaging clos...

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, C...

You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug...

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies...

As a Silicon Design Engineer in the AMD AECG ASIC TFM (tools Flows Methodology) team, you will work with design experts (FE and BE) to come up with the best implementation methodologies/flows and work on development and support of the FE/BE flows. KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physica...