600 Timing Closure Jobs - Page 12

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum of 7+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

: Arm s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arms soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities: Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE-targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience: This role is for a Senior DFT Engineer with 8+ years of proven experience in Design for Test Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Core DFT skills considered crucial for this position should include some of the following: Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools Nice To Have Skills and Experience: Familiarity with IEEE 1149, 1500, 1687 Familiarity with Synthesis and Static Timing Analysis Working knowledge of Siemens DFT tools Ability to work both collaboratively on a team and independently. Innovative and a passion for progress Hard-working and excellent time management skills with an ability to multi-task In Return: Opportunity to work with some of the greatest minds in the industry! Competitive compensation and great benefits! Flexible working hours #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

The position available involves working with Samsung Semiconductor India Research (SSIR), an innovative hub focused on developing cutting-edge semiconductor solutions. As part of one of the largest R&D centers for Samsung Electronics outside Korea, you will have the opportunity to work on advanced technologies in System LSI, Memory, Foundry, and more. Your role will entail collaborating on diverse projects, conducting research in emerging technology areas, and contributing to the development of world-class products. We are seeking a professional with over 5 years of experience in full chip Design for Testability (DFT) architecture, implementation, timing closure, and post-silicon validation. Your expertise should cover areas such as scan architecture planning, MBIST architecture, analog and mixed-signal IP testing, and timing closure for various test modes. You should be adept at leading a team, coordinating with RTL and physical design teams, and managing project timelines effectively. The ideal candidate will hold a B.Tech/B.E/M.Tech/M.E degree with a strong background in DFT methodologies. Knowledge of JTAG operation, iJTAG protocol, and functional testing is essential for this role. Additionally, you should have a proactive approach to identifying risks, troubleshooting timing issues, and ensuring high reliability and performance in semiconductor testing. Samsung Semiconductor India Research (SSIR) is committed to fostering a diverse and inclusive work environment, offering Equal Employment Opportunity to all individuals. Regardless of your background, SSIR values creativity, innovation, and a collaborative spirit in driving technological advancements. If you meet the qualifications and are excited about working on cutting-edge technologies with a global leader in semiconductor solutions, we encourage you to apply for this challenging and rewarding opportunity.,

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 8+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers. Medical Insurance and a cohort of Wellness Benefits Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Roles and Responsibility Senior IO-MMU Design Engineer Role Overview: Leads the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Key Responsibilities: Architect and implement RTL for IO-MMU subsystems Define IO translation and access control logic Collaborate with SoC, interconnect, and virtual memory teams Ensure compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR) Deliver Lint, CDC, synthesis, and DFT clean designs Required Skills: 8+ years of experience in SoC and IP-level RTL design Strong in SystemVerilog, with knowledge of memory protection and address translation Experience with SoC virtual memory systems and PCIe/AXI protocols Familiar with coherency, TLB, page walk and IOVA mechanisms Skilled in timing closure and formal/CDC tools

Qualcomm India Private Limited is seeking a Software Engineer with expertise in various aspects of System on Chip (SoC) architecture and design. In this role, you will be responsible for working with AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. An understanding of Memory controller designs and microprocessors is considered an added advantage for this position. As a Software Engineer at Qualcomm, you will be required to have hands-on experience in constraint development and timing closure. Additionally, you will collaborate closely with the SoC verification and validation teams for pre/post Silicon debug. Proficiency in Low power SoC design, Synthesis, Multi Clock designs, and Asynchronous interface is crucial for this role. Experience in using tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is also a requirement. The ideal candidate for this position should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, along with at least 2 years of Software Engineering experience. Alternatively, a Master's degree with 1+ year of relevant work experience or a PhD in a related field is also acceptable. A minimum of 2 years of academic or work experience with Programming Languages like C, C++, Java, Python, etc., is necessary for this role. Qualcomm is an equal opportunity employer that is committed to providing an accessible process for individuals with disabilities who may need accommodations during the application/hiring process. If you require an accommodation, you may contact Qualcomm through the provided email address or toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For any inquiries about this role, please contact Qualcomm Careers directly.,

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. As part of the team, you will be responsible for various key tasks including scan architecture planning, pin mixing, scan compression planning, and optimization for pattern volume for SA and TD pattern sets. Your expertise will be crucial in scan synthesis, power optimization techniques in test modes, MBIST architecture planning, repair architectures, insertion, verification, and analog and mixed signal IP testing architecture and verification. In this role, you will also be involved in timing closure of scan, MBIST, and other test modes, writing SDCs, understanding timing exceptions, debugging timing issues with the PD team, performing timing GLS, and debugging fails in simulations. Post-silicon validation, interpretation of tester results, debugging IR drop issues, and diagnostics of silicon failures will also be within your scope of responsibilities. Understanding of JTAG operation and debug is required, with knowledge of iJTAG protocol being desirable. Additionally, you will need to understand functional test cases, IO testing, and testing of ARM processor cores. As a Senior DFT Engineer, you must demonstrate the ability to lead a team across all aspects of DFT, interact effectively with RTL and physical design teams for DFT implementation, anticipate risks, plan project timelines, and milestones. The role requires a Bachelor's or Master's degree in Engineering with 5+ years of relevant experience. Samsung Semiconductor India Research (SSIR) values diversity and is committed to providing Equal Employment Opportunity to all individuals, irrespective of their religion, gender, age, marital status, gender identity, veteran status, genetic information, disability status, or any other characteristic protected by law.,

You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Additionally, you must have floorplan-based synthesis knowledge like DCG, and work closely with RTL designers on constraints debug and feedback on a constant basis. Your responsibilities will include pre-layout timing analysis and reporting, post-layout timing analysis for placement, CTS & PRO, clock gating checks, and timing closure. You should also have experience in ECOs and final tapeout timing closure skills across corners and modes. Collaboration with RTL design team, PD team, and HMs team for overall timing closure for SoC is crucial. Having knowledge of Primetime and Tempus is essential, along with expertise in leakage recovery, Vmin targets, and performance versus leakage trade-off for final sign-off. Deep scripting knowledge is required, as well as soft skills for working effectively with stakeholders. About the Company: 7Rays Semiconductors (https://7rayssemi.com/) is a provider of end-to-end custom SoC design solutions, covering SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company is dedicated to assisting top semiconductor and system companies in designing their complex SoCs. At 7Rays Semiconductors, we focus on establishing strong partnerships with our clients to deliver high-quality solutions tailored to their specific needs. With a skilled engineering team and a successful track record in project execution, we prioritize excellence and innovation in SoC Design, Development, and deployment of customers" products.,

AMRITSAR GROUP OF COLLEGES is looking for Assistant Placement Officer to join our dynamic team and embark on a rewarding career journey. Career Counseling : Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals. Job Placement : Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences. Employer Engagement : Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements. Job Postings and Recruitment : Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures. Resume and Interview Preparation : Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job. Internship and Training Opportunities : Identify and promote internship and training opportunities for students and job seekers to gain practical experience. Networking Events : Organize job fairs, networking events, and industry - specific workshops to connect candidates with potential employers.

PHYSICAL DESIGN ENGINEER (4 6 YEARS) - Incise & CMI (Cornell Medical Instruments) PHYSICAL DESIGN ENGINEER (4 6 YEARS) 2025-04-18T06:11:54+00:00 Skills : Calibre,ICC2,Perl,TCL Job Locations : Hyderabad Total vacancies : 3 Experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on Floor-planning, Place & route, power and clock distribution, pin placement. In-depth knowledge on industry leading tools like Redhawk, Olympus/ICC2, Primetime, and Calibre Knowledge of package modeling, package and chip level analysis is added advantage Good understanding of Physical design verification using Calibre. Knowledge of Synthesis and DFT is added advantage. Prior experience with 16nm or finer geometries is a plus. Proficient use of tcl/Perl Must have good communication skills and self-driven individual. To apply for . Our team will contact you for further details. Job Category: PHYSICAL DESIGN ENGINEER Job Type: Full Time Job Location: Hyderabad Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with the storage and handling of your data by this website. *

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: VLSI Physical Design Planning. Experience: 8-10 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route Experience: 3-5 Years

The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor or Master degree in Electronics 48 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

You will be part of a Physical Design / Timing Closure team for projects with GHz frequency range and cutting-edge technologies. Your primary responsibility will involve developing timing constraints for full chip or block level designs. Additionally, you will be accountable for STA signoff for complex multi-clock, multi-voltage SoCs. Your role will entail Synthesis, Timing Analysis (STA), and Clock Tree Synthesis (CTS) at Full Chip or block level, particularly focusing on Lower tech nodes below 14nm. To excel in this role, you should hold a B. Tech. / M. Tech. degree with 4-10 years of experience in Synthesis and STA. Your expertise should extend to the synthesis of complex SoCs at block/top levels and crafting timing constraints for intricate designs featuring multiple clocks and voltage domains. Previous experience in pre and post-layout timing analysis and proficiently resolving associated issues is crucial. Moreover, you should possess hands-on experience in post-layout timing closure for multiple tape outs, encompassing timing Engineering Change Orders (ECOs) and STA signoff. Demonstrated proficiency in developing I/O constraints for various Industry standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, among others, is highly desirable. Your technical skills should extend to working on technology nodes like 28nm, 20nm, 14nm, and 10nm. A good understanding of Electronic Design Automation (EDA) tools like RC, DC, PT, and PTSI is essential. Furthermore, your role may involve formal verification of RTL-to-netlist and netlist-to-netlist with Design-for-Testability (DFT) constraints. A solid grasp of VLSI processes, device characteristics, deep submicron parasitic effects, crosstalk effects, etc., is expected. Proficiency in TCL and Perl scripting will be advantageous to perform the tasks effectively. Overall, as an STA Engineer specializing in Timing Closure and Synthesis, you will play a crucial role in ensuring the successful completion of projects involving advanced technologies and stringent timing requirements.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Design Planning. Experience: 1-3 Years.

Experience in handling STA of multi-power domain designs & constraint mode merging. Job Description In your new role you will: Defining and verification of STA constraint for Functional and Test/SCANModes. Defining PVT s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Your Profile You are best equipped for this task if you have: BE/B.Tech/M.Tech with 8+ years. Project leading knowledge is preferred. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations. Independently, hands-on STA lead of projects. Experience in handling STA of multi-power domain designs & constraint mode merging. STA flow development , abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction inmulti-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Interface to design team and PD team and drive TAT reduction for PD. Has experience in mentoring junior engineers. Proficient with EDA tools from Synopsys/Cadence . Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Manage all student progress and prepare required strategies to overcome issues. Arranging for guest lectures. Arranging visits to the local parlors for the students. Arranging Induction & different sessions too. Looking after placements for students of hub center Maintaining pre placement and post-placement data and sharing it with the central office. Checking the quality of training at the centers and submitting reports about the same. Taking an initiative in creating new placement partnerships and tie ups in coordination with the Central team. Track the students for the complete period of their employment in the city. Provide mentor-ship support to students employed in the region to help them settle down including counseling, helping with finding accommodation, resolving issues with employers, helping establish social network in city, providing any other emergency support in the city Capture feedback of students and recruiters on an ongoing basis. Build and maintain regular connections with current and past employers & clients. Requirements Willingness to travel regularly Minimum Qualification Graduation 1 years of experience in the field Own two wheeler with required documents Basic Computer knowledge (Microsoft Excel & Word, Internet, etc.) Good Communications Skills Fluency in English, Hindi & the Regional Language (Kannad) Experience/ interest in training, teaching & coordinating.

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: VLSI Physical Design Planning.Experience8-10 Years.

Job Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer (4+ Years) to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 2 nm/3nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , Synopsys ICC2 , Primetime , RedHawk , etc. Handle congestion analysis , design optimization , and area/power/timing trade-offs to meet PPA targets. Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff. Contribute to timing closure , ECO implementation, and physical sign-off.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

About The Role Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years About Accenture Combining unmatched experience and specialized skills across more than 40 industries, we offer Strategy and Consulting, Technology and Operations services, and Accenture Song all powered by the worlds largest network of Advanced Technology and Intelligent Operations centers. Our 699,000 people deliver on the promise of technology and human ingenuity every day, serving clients in more than 120 countries. Visit us at www.accenture.com What would you do "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for "Agility for quick learningAbility to work well in a teamProcess-orientationWritten and verbal communicationNetwork fundamentalsUnderstanding all the networking devices:Routers, switches, etc.IP connectivity, access, addressing, and servicesNetwork security fundamentalsInstallation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business NetworksExcellent CommunicationProblem Solving SkillsFlexibilityTeamworkExperience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: "In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shiftsProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - FamiliarityProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the outputManage client s optical network, manage alarms and faults in a multi-vendor environment, andTracking of all work in ticketing system network interconnects with internal and external network operatorsTrack and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providersManage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary.Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacementRead/Parse vendor notifications and translate to Clients Production Change Request (PCR s)Look up affected circuits to include them in change requestEscalate any emergency change requests for immediate review and schedulingNavigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

Positions are open for full-time and co-op/internship in the areas of CPU and SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff. Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA. Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. Requirements Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master s Degree or Bachelor s Degree in technical subject area.