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PCIe/CXL Design Tech Lead Altera

6.0 - 9.0 years

0 Lacs

Bengaluru, Karnataka, India

On-site

Job Details Job Description: Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node. Develops logic/RTL design and simulation for IP/SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timi...

Posted 4 months ago

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