690 Timing Analysis Jobs - Page 7

Recruiting is a specialized area of staffing and recruiting focused on attracting and placing prospective employees including: Promoting the organizations image as a desirable place to work Attracting, recruiting, screening, and interviewing candidates Recommending placement of internal and external candidates for entry-level and experienced positions Referring applicants for particular job openings, administering pre-employment tests, checking references, conducting exit interviews for candidates declining offers, and providing feedback to unsuccessful candidates May assist with job advertising and postingPositions on this level are fully proficient in executing established standards. Works...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

Alternate Job Titles: ASIC Digital Design, Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced digital design engineer with a deep-rooted curiosity for advancing technology. With a strong foundation in RTL coding, microarchitecture, and high-speed digital IP, you thrive on tacklin...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise ...

As a Hardware Board PCB design engineer at A&W Engineering Works, your role will involve leveraging your skills and knowledge in hardware product development cycles. You will be responsible for designing high-speed boards and working with various protocols such as PCIe, USB3.0, MIPI CSI/DSI, LVDS, HDMI, DDR3/4, SD/eMMC, NAND, SPI/I2C. Additionally, you will work with peripherals like Image sensors, LCD displays, and Flash memory. Key Responsibilities: - Work on various stages of hardware product development cycles - Design high-speed boards and work with protocols like PCIe, USB3.0, MIPI CSI/DSI, etc. - Work with peripherals such as Image sensors, LCD displays, and Flash memory - Conduct Tim...

Job Title: STA Design Engineer (Backend) Location: Bangalore Experience: 5+ Years Job Description: We are looking for an experienced STA Design Engineer with strong expertise in Static Timing Analysis (STA) for ASIC/SoC backend design. The candidate should have hands-on experience in timing closure, signoff methodologies, and working closely with physical design and RTL design teams to deliver high-quality silicon. Key Responsibilities: Perform Static Timing Analysis (STA) across multiple process, voltage, and temperature (PVT) corners. Drive timing closure at block and full-chip level. Work on constraint development, validation, and optimization (SDC files). Perform setup, hold, recovery, a...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutio...

Role Overview We are expanding our team in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems You will collaborate across analog and digital teams to deliver high-performance, reliable solutions for next-generation automotive networks Required Skills + BS/MS/BTech/M Tech in Electrical Engineering or related field + 8+ years of experience in digital design for communication systems + Expertise in Verilog/SystemVerilog, Ethernet or similar protocols, and PHY layer design + Strong understanding of PLLs, clocking schemes, and timing closure + Experience with analog IP int...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys...

Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR...

You have 24 years of experience in ASIC Physical Design and Timing Analysis. Your hands-on expertise includes working with tools such as: - Physical Design: Innovus, ICC2, Fusion Compiler, or similar - STA: PrimeTime, Tempus - Physical Verification: Calibre, Pegasus Open positions available: - PD- 2-4 years (Chennai) - STA - Top level or Fullchip - 4+ years (Bangalore/Pune/Hyderabad) You should have an immediate to 30 days notice period.,

As a Hardware Engineer at Qualcomm India Private Limited, your role involves planning, designing, optimizing, verifying, and testing electronic systems for cutting-edge products. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. **Key Responsibilities:** - STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus. - Running Primetime and/or Tempus for STA flow optimization and...

As a Qualcomm Hardware Engineer, you will be responsible for the following: - STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus. - Utilize Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. - Evaluate multiple timing methodologies/tools on different designs and technology nodes. - Develop automation scripts within STA/PD tools for methodology enhancement. - Demonstrate good technical writing and communication skills while working in a cross-collaborative environment. - Experience in design automation using TCL/Perl/Python. - Fam...

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....

Role Overview: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will collaborate with design experts to develop the best implementation methodologies and flows for the BE flows. Key Responsibilities: - Define and drive key Backend/Physical Design methodologies. - Collaborate with AMD CAD Teams, Design team, and physical design teams to ensure smooth end-to-end design flows. - Assist in defining roadmaps for existing flows and provide technical support for challenging technical debug. - Gather requirements from design teams and devise strategies to address critical technical issues. - Engage in Floor-plan, Physical Implementation of Power-plan, Synthes...

Role Overview: As the ASIC Back-End Head at Wipro Limited, your primary responsibility will be to lead the physical design and implementation of Application-Specific Integrated Circuits (ASICs). You will be tasked with ensuring optimal performance, power efficiency, and manufacturability of ASICs. Key Responsibilities: - Define and execute the ASIC back-end design roadmap with a strategic approach. - Oversee the RTL to GDSII flow management, including synthesis, floorplanning, placement, routing, timing closure, and sign-off. - Ensure Physical Design Optimization by meeting Power, Performance, and Area (PPA) targets. - Utilize EDA Tool Expertise by working with Synopsys, Cadence, and Mentor ...

You are a highly skilled and experienced Full Chip RTL Design Architect sought by the company to join their dynamic team. Your role involves a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. You will be pivotal in defining and implementing full chip-level RTL designs to ensure successful execution. - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications and ensure seamless implementation. - Develop and opt...

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design , floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design, methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. Your Profile You are best equipped for this task if you have: Hands-on experience in physica...

Expertise in ABAP and ABAP on HANA and oData Experience with analysis tools like Run time analysis, SQL Trace, code inspector and SAP ABAP Test Cockpit to check the quality of the ABAP code and optimize for SAP HANA. ABAP code pushdown and Data modelling, CDS views and AMDP Experience in correcting customer exit changes after upgrade/migration of SAP S/4 HANA. Hands-on Experience on SAP ECC on HANA migration projects Transform traditional ABAP programs in legacy SAP system into S/4 HANA architecture. Design and implement CDS and AMDP based on the business requirement.Adobe forms development in S/4 HANA (Online and Offline scenarios)Compile Technical Specification document for all the develop...

As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Utilize your 3 to 5 years of experience in static timing analysis, constraints, and other physical implementation aspects - Demonstrate a solid understanding of industry standard tools such as PT, Tempus, and familia...

**Role Overview:** At EdgeCortix, a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design, your role as a member of the Artificial Intelligence Hardware Team involves owning the IP integration into ASSP/SOC, integrating EdgeCortix DNA IP and other third-party IP, and contributing to the development of verification infrastructure. You will play a crucial role in enhancing the energy efficiency for AI inference at the edge, aiming for cloud-level performance on small to medium form factor devices. **Key Responsibilities:** - Own the IP integration into ASSP/SOC - Integrate EdgeCortix DNA IP and other third-party IP - Expe...

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...