464 Timing Analysis Jobs - Page 4

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and in...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

At Cadence, we are seeking a Verification Engineer to join our team dedicated to the Protium Enterprise Level Prototyping Platform. In this role, you will be responsible for running and analyzing the regression suites regularly for Protium. Your main tasks will include debugging regression suites, building expertise in Protium flows, and supporting other team members with test runs. It is essential to have a deep understanding of the existing RTL for test cases, debug functional failures, and identify check-ins to address bugs promptly. Key Requirements: - A B.Tech/M.Tech degree in Electrical Engineering with a strong foundation in Digital Logic Systems and Timing Analysis. - Proficiency in ...

ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and pref...

Alternate Job Titles: ASIC Digital Design, Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced digital design engineer with a deep-rooted curiosity for advancing technology. With a strong foundation in RTL coding, microarchitecture, and high-speed digital IP, you thrive on tacklin...

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to...

As a Physical Design Engineer at Google, you will play a crucial role in developing custom silicon solutions that drive the future of Google's consumer products. Your work will contribute to the innovation behind widely loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with 5 years of experience in timing analysis and physical design, you will bring a solid foundation to the team. Additionally, experience in scripting languages such as Perl, TCL, Python is required. Your responsibilities will include ...

Are you ready for a career that presents challenges while also instilling a sense of pride in your work At Ambit, we provide an ideal platform for individuals to work and advance in the field of semiconductor design. Our employees enjoy the freedom to work in their own adaptable ways, with the necessary support to continue learning and improving their skills. We firmly believe that in order for a company to achieve significant growth through innovation, its employees must be empowered to experiment and innovate freely. The positive and vibrant work environment at Ambit reflects our management's dedication to our employees and their values. Join us today for a promising future in semiconducto...

Postition Summary This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work...

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

Role: Design Analysis Engineer (FPGA/Vivado) [M.Tech Mandatory] What they do: Analyze design issues in Vivado implementation flow. Apply and debug timing constraints to ensure design closure. Propose/design corrections to fix issues. Use scripting (Shell/Python/TCL) to automate and improve analysis. (RTL/Verilog knowledge is optional, not mandatory.) Mandatory Skills: Strong in Timing Constraints (STA concepts) Hands-on with Vivado tool flow Shell/Python/TCL scripting for automation Good to have: Quartus exposure Basic RTL/Verilog understanding In short: This is not an RTL coding role. Its a timing + Vivado design analysis role with scripting. Feel free to share the resume if you feel its a ...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

As an ASIC Digital Design Engineer at Synopsys, you play a crucial role in designing and developing high-performance digital designs at both chip and block levels. Your robust understanding of digital design principles and experience in RTL coding and simulation are key to driving the success of cutting-edge silicon chips that power innovative applications. Collaborating with verification teams, you ensure thorough testing and validation of designs while analyzing and optimizing design performance, power, and area metrics. Your proactive problem-solving skills and detail-oriented approach enable you to contribute effectively in design reviews, providing constructive feedback to peers. Workin...

As an FPGA Design Engineer, you will be responsible for utilizing your expertise in VHDL/Verilog/System Verilog, RTL design, and FPGA design tools to develop FPGA solutions. Your responsibilities will include managing the complete FPGA development flow, from logic design to validation, using tools such as Lattice/Altera FPGA families. You will have the opportunity to work on debugging and troubleshooting FPGA implementations on hardware boards, as well as gaining experience with communication protocols and bus interfaces. To qualify for this role, you should hold a Bachelors/Masters degree in Electrical Engineering, Computer Science, or a related field. Your proven experience in FPGA develop...

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this...

Key Responsibilities: Support the configuration and testing of Oracle HCM Cloud Payroll or Time and Labor (OTL) modules. Assist in gathering client requirements and translating them into system configurations and business process flows. Help in preparing functional documentation, test scripts (SIT & UAT), and user guides. Participate in payroll/OTL setup activities such as element creation, time entry rules, fast formulas, and validation rules. Analyze time and attendance or payroll processing scenarios and support issue resolution. Perform data validation and assist in data migration from legacy systems. Collaborate with cross-functional teams including HR, Finance, and IT.

This is what you are responsible for Develop verification environments for modules, subsystems, top level and FPGA Build models, checkers and random test frameworks using SystemVerilog and UVM Participate in Low power analysis (UPF), power estimation, C modeling Perform lint, CDC, code coverage, functional coverage Formal verification of modules using SVA assertions Necessary Qualifications Experience in verifying complex subsystems and ASICs Experience with building scalable verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, and board debug BTech/MTech in E...

You will work with some of the brightest people you'll ever meet. Engineers, Analysts, and Product owners collaborate to identify, develop, and maintain world-class financial solutions. Your responsibilities will include creating and sourcing a wide variety of designs for implementation and validation on FPGA boards, system-level integration and testing, timing closure of FPGA Designs, and developing methodologies for HW validation for different types of designs. Desired Skills: - A four-year degree in ECE/EEE, VLSI Design, or a related field, or equivalent training/experience - Knowledge in Logic design /RTL coding using Verilog, System Verilog, or VHDL - Hands-on expertise in Multi Clock d...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's deg...

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in ...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)