694 Timing Analysis Jobs - Page 10

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

As a Hardware Engineer at Qualcomm India Private Limited, your primary responsibilities will include: - Setting up, converging, reviewing, and signing off on multi-mode, multi-voltage domain designs. - Conducting timing analysis, validation, and debugging across multiple PVT conditions using PT/Tempus. - Running Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. - Evaluating multiple timing methodologies/tools on different designs and technology nodes. - Working on automation scripts within STA/PD tools for methodology development. - Demonstrating good technical writing and communication skills and being willing to work in a cross-collaborative environment. - Uti...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Responsibilities: * Design, test & verify physical designs using Primetime, Innovus & PNR. * Collaborate with cross-functional teams on floor planning & timing closure.

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metast...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Coll...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

We are seeking an experienced ASIC Physical Designer to join our team in Hyderabad. The successful candidate will be responsible for designing and implementing complex ASICs, ensuring timely and efficient physical design closure.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS Product Engineer The Product Engineer position is in the Customer Enablement and Succes...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The role will involve : .Writing designs using Verilog/System Verilog / C / C++ / TCL for functional and performance testing ofoverall Protium flow. . Performance and functional validation of multiple features on Protium. .Hands on debug and the ability to converge on feature delivery. . Provide feedback to the development team and work with the team for new feature development. Key requirements: 1. (EE) -must have a very good understanding ofDigital Logic Systems /Timing Analysis etc. 2. Hands-on knowledge of Verilog and System Verilog is a must. 3. Must have good analyticaland prob...

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to ...

Good understanding of signal integrity and power integrity principles Signal integrity extraction/3D models generation experience Cadence, HFSS and Siemens Advanced Solvers Expertise in circuit simulation with different tools such as Hspice, ADS, Cadence TopXp System level SI simulation using simulation tools Tools Used : Cadence PowerSI/ Agilent ADS/ Siemens Advanced Solver/Allegro SIP/Ansys SI wave, HFSS Expertise in circuit simulation with different tools such as Hspice and ADS. Experience Requirements 5-7 years of experience in SI/PI area Experience in board/package design SI/PI analysis Proven ability to use modern tools for S-parameter extraction of board/package Additional skills Prog...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

Excellent Communication Proficiency in collaboration and delegation of duties Hands on - Google sheet, forms & drives Flexible with work timings & Male candidate is preferred Follow ups on tasks and activity.

Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in futur...

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, ti...

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology no...

Assist in managing end-to-end recruitment, onboarding, and induction processes. Support employee engagement activities and performance appraisal cycles. Maintain and update employee records, HRIS systems, and payroll inputs.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of exper...

Seeking an experienced Delivery Lead to oversee the overall service delivery management for our Oracle Managed Services project. The Delivery Lead will ensure adherence to Service Levels described in the agreement and collaborate closely with the client's Service Delivery management personnel. The role involves managing the compilation of metrics around open tickets, backlog, aging, etc., and driving metrics-driven continuous improvement and customer satisfaction. Responsibilities: Oversee overall service delivery management. Ensure adherence to Service Levels. Collaborate with client Service Delivery management personnel. Manage the compilation of metrics around open tickets, backlog, aging...

Seeking an experienced Delivery Lead to oversee the overall service delivery management for our Oracle Managed Services project. The Delivery Lead will ensure adherence to Service Levels described in the agreement and collaborate closely with the client's Service Delivery management personnel. The role involves managing the compilation of metrics around open tickets, backlog, aging, etc., and driving metrics-driven continuous improvement and customer satisfaction. Responsibilities: Oversee overall service delivery management. Ensure adherence to Service Levels. Collaborate with client Service Delivery management personnel. Manage the compilation of metrics around open tickets, backlog, aging...

Required skills: Job Description: Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, ...