The Nanopore Site

Role Overview: As a Layout Design Engineer, your main role will involve hands-on experience with layouts of important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in a compiler context. You should have worked on 16nm / 14nm / 10nm / 7nm / Finfet process technologies. Additionally, you should have hands-on experience with top-level memory integration and expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. A good handle on IR/EM related issues in memory layouts is also essential. Key Responsibilities: - Work on layouts of memory building blocks in a compiler context - Ensure top-level memory integration and perform DRC, LVS, Density verification - Address IR/EM related issues in memory layouts - Collaborate with external customers and cross-functional teams Qualifications Required: - 2-4 years of relevant experience - Proficiency in Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks - Strong knowledge of ultra-deep sub-micron layout design challenges and understanding of DFM guidelines - Experience or strong interest in memory compilers development - Excellent team player with demonstrated ability to work effectively in a team environment Location: Bangalore If you meet the above requirements and are interested in this opportunity, please send your resumes to hr@smartvlsi.com.,