10 Testplan Development Jobs

As a highly motivated and energetic Individual Contributor, you will drive roadmaps for the IP / SS domain, focusing on the complete IP portfolio. You will delve deeper into logic design and architecting, developing complex IPs and Subsystems solutions. You will collaborate closely with a team of global experts in Systems and SoC Design to tackle design and architectural challenges within the complex IP and overall System level solutions. Your work will span a wide spectrum of skills, from developing high-level Specifications to actual design Implementation. Key Responsibilities: - Own and drive Roadmaps for the complete IP / Subsystem domains portfolio within the global R&D team. - Perform ...

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for micro-architecture development, RTL design, and front-end flows. Your key responsibilities will include: - Mirco architecture & RTL development and its validation for linting, clock-domain crossing, and DFT rules. - Working with the functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. - Hands-on experience in constraint development and timing closure. - UPF writing, power-aware equivalence checks, and low power checks. - Supporting performance debugs and addressing performance bottlenecks. - Providing support to sub-system, SoC integrati...

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for the micro-architecture development, RTL design, and validation for linting, clock-domain crossing, and DFT rules. Your expertise will be utilized in working with the functional verification team on test-plan development and waveform debugs at core, sub-system, and SoCs levels. Additionally, you will play a crucial role in constraint development, timing closure, UPF writing, power-aware equivalence checks, and low power checks. Your support will be vital in performance debugs and addressing performance bottlenecks, as well as providing assistance to sub-system, SoC integration, and chip level...

**Job Description:** As a **Verification Engineer** at MaxvyTech in Bangalore, you will be responsible for the following key responsibilities: - Utilize your experience in Verilog, SystemVerilog, and UVM to design and develop test plans. - Develop test cases in UVM/SV and C languages. - Demonstrate the ability to work independently to develop drive/monitor code. **Qualifications Required:** - Bachelor's or Master's degree in Engineering, preferably in B.E. or M.Tech. - Proficiency in APB, AXI, and AHB protocols. - Familiarity with MIPI protocol will be an added advantage. - Knowledge of scripting languages such as Perl and Python. If you are looking to join a dynamic team and contribute to c...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Senior Design Verification Engineer The Engineering Enablement team is responsibl...

As an Individual Contributor in the IP / SS domain, your role involves driving roadmaps for the complete IP portfolio, focusing on logic design and architecting Complex IPs / Subsystems solutions. You will collaborate with a team of global experts to address design challenges and work on a wide spectrum of skills from high-level specifications to actual design implementation. **Key Responsibilities:** - Own and drive Roadmaps for complete IP / Subsystem domains portfolio within the global R&D team. - Perform benchmarks against industry players to ensure innovative features for customers. - Architect and Design complex IP and Subsystems for Automotive Self Driving Vehicles (ADAS), In-Vehicle ...

You should have a minimum of 1 year of experience and hold a B.E or M.Tech degree. Your role will involve working with Verilog, SystemVerilog, and UVM, designing and developing test plans, and creating test cases in UVM/SV,C. You should be comfortable working independently to develop Drive/Monitor code. It is essential for you to have knowledge of APB/AXI/AHB protocols, and familiarity with MIPI protocol would be an added advantage. Additionally, proficiency in Perl and Python is required. If you meet the requirements and are interested in the position, please send your resume to jobs@maxvytech.com with the job title you are applying for. The salary offered for this position is 3 LPA.,

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Mult...

You are a highly motivated and energetic individual with a team-oriented approach, responsible for driving roadmaps in the IP/Subsystem domain. Your role involves delving deep into logic design, architecting, and developing complex IPs/Subsystems solutions. Working closely with a team of global experts in Systems and SoC Design functions, you will lead or address design/architectural challenges within the context of complex IPs and overall system level solutions. Your tasks will range from developing high-level specifications to actual design implementation. Your key responsibilities include owning and driving roadmaps for the complete IP/Subsystem domains portfolio within the global R&D tea...

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal persp...