4 Testplan Development Jobs

You should have a minimum of 1 year of experience and hold a B.E or M.Tech degree. Your role will involve working with Verilog, SystemVerilog, and UVM, designing and developing test plans, and creating test cases in UVM/SV,C. You should be comfortable working independently to develop Drive/Monitor code. It is essential for you to have knowledge of APB/AXI/AHB protocols, and familiarity with MIPI protocol would be an added advantage. Additionally, proficiency in Perl and Python is required. If you meet the requirements and are interested in the position, please send your resume to jobs@maxvytech.com with the job title you are applying for. The salary offered for this position is 3 LPA.,

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Multi Clock designs, Asynchronous interface, and Low power SoC design is essential for this role. Your key responsibilities will involve micro-architecture & RTL development, validation for linting, clock-domain crossing, and DFT rules. You will work closely with the functional verification team on test-plan development and waveform debugs at various levels. Experience in constraint development, timing closure, UPF writing, power aware equivalence checks, and low power checks is required. Additionally, you will be supporting performance debugs and addressing performance bottlenecks, along with providing assistance in sub-system, SoC integration, and chip-level debug. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. If you meet the following qualifications and have the required experience, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

You are a highly motivated and energetic individual with a team-oriented approach, responsible for driving roadmaps in the IP/Subsystem domain. Your role involves delving deep into logic design, architecting, and developing complex IPs/Subsystems solutions. Working closely with a team of global experts in Systems and SoC Design functions, you will lead or address design/architectural challenges within the context of complex IPs and overall system level solutions. Your tasks will range from developing high-level specifications to actual design implementation. Your key responsibilities include owning and driving roadmaps for the complete IP/Subsystem domains portfolio within the global R&D team. You will perform benchmarks against other industry players to ensure differentiating features for customers with a high level of innovation. Architecting and designing complex IPs and Subsystems across various protocols required for Edge processing, Automotive Self-Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail-Safe Subsystems (ASIL-D), etc., will be part of your role. You will be responsible for leading IPs/Subsystems from concept to design and development, achieving final design performance in an integrated system within aggressive, market-driven schedules. Ensuring quality adherence throughout the IP development cycle, analyzing existing processes, recommending and implementing process improvements, and driving and mentoring teams towards achieving Zero Defect designs are crucial aspects of your role. Additionally, you will be responsible for owning and driving global IP design methodologies across sites with global stakeholders. As a self-starter with over 18 years of experience, you should be able to architect and design complex IP designs/Subsystems with minimal supervision. Your expertise should include custom processor designs with key DSP functions, processor designs like RISC-V Core, cache-based subsystems, high-speed serial protocols, and associated challenges, understanding of key external memory interface protocols, microcontroller architecture, bus protocols, HDLs, scripting languages, and C/C++ for hardware modeling. Knowledge of end-to-end IP development flow, testbench and testplan development, and pre-silicon validation using FPGA/Emulation Board would be advantageous. In terms of soft skills, you should possess proficient skills in both written and verbal communication, with the ability to articulate well. Demonstrating a sense of ownership, engaging everyone with trust and respect, showcasing emotional intelligence, and embodying leadership values are essential for success in this role. You should have the ability to work effectively as part of a team, whether local, remote, or multisite.,

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,