2 Tcsh Jobs

As a Sr. Engineer in ASIC Verification at Synopsys, you will play a crucial role in ensuring the robustness and reliability of our digital designs through meticulous verification processes. Your expertise in high-speed protocols and strong foundation in Verilog, VHDL, and/or SystemVerilog will empower you to identify verification environment requirements and develop complex UVM verification environments. Your proactive approach to problem-solving and excellent communication skills will enable you to collaborate effectively with cross-functional teams and contribute to the success of our cutting-edge projects. Your responsibilities will include generating verification test plans, defining and verifying complex UVM verification environments, evaluating various aspects of the development flow, and identifying design problems to propose corrective actions. By enhancing the overall quality and performance of our silicon IP products, you will help drive continuous improvements in our verification methodologies and practices. Your passion for learning and exploring new technologies, coupled with your 3+ years of relevant experience in ASIC digital verification, will be instrumental in supporting the growth and success of both our projects and Synopsys as a whole. You will be part of an experienced and dedicated digital design and verification team at Synopsys, where excellence and continuous improvement are key priorities. Working in a dynamic and fast-paced environment, you will have the opportunity to collaborate with experts in various fields, learn from their insights, and contribute significantly to the success of our innovative projects. If you are a detail-oriented, innovative engineer with a proven desire to explore new technologies and a proactive approach to addressing challenges, we invite you to join us in shaping the future through continuous technological innovation. In return for your contributions, we offer a comprehensive range of health, wellness, and financial benefits tailored to meet your needs. Your recruiter will provide detailed information about the salary range and benefits during the hiring process. If you are ready to make a meaningful impact in the Era of Smart Everything, we look forward to welcoming you to our team at Synopsys.,

Job Titles: Senior Staff ASIC Verification Engineer- Pune Location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and passionate ASIC Digital Verification engineer, ready to take on technical leadership in a dynamic, high-impact environment. With a proven track record of developing and validating complex UVM verification environments, you thrive in collaborative settings and enjoy mentoring others. You bring a deep understanding of digital verification flows, simulation, and coverage analysis, and you excel at identifying and solving challenging design problems. Your experience spans 8-15+ years in ASIC verification, where you&aposve consistently demonstrated your ability to architect, plan, and execute verification strategies. Youre comfortable multitasking between multiple projects and have a genuine desire to stay at the forefront of emerging technologies. You communicate effectively in both written and spoken English, and your organizational skills help ensure that projects are delivered on time and to the highest quality standards. Youre motivated by the opportunity to make a significant impact, not just through your own work, but by elevating the entire team around you. Your proactive approach to learning, problem-solving, and process improvement defines your professional ethos. What Youll Be Doing: Identify verification environment requirements from specifications, design functionalities, and interfaces. Generate comprehensive verification test plans and maintain detailed documentation for verification environments and their usage. Define, develop, and verify advanced UVM (Universal Verification Methodology) environments for complex ASIC designs. Evaluate and exercise all aspects of the verification flow, including Verilog/SystemVerilog development, functional simulation, constraint development, behavioral modeling, and coverage metrics analysis (functional and code coverage). Collaborate closely with architects, designers, and the VIP team to ensure seamless integration and accomplishment of project goals. Identify design problems, propose corrective actions, and resolve inconsistencies in documented functionalities. Mentor and guide junior engineers, supporting them in debugging and solving complex verification problems. Support customer issues through issue reproduction and in-depth analysis, ensuring customer satisfaction. Drive continuous improvement of verification methodologies and execution efficiency within the team. Adhere to best practices, quality standards, and maintain a high level of test and verification rigor. The Impact You Will Have: Accelerate the delivery of robust, high-quality ASIC products by ensuring thorough and systematic verification. Enhance the teams technical capabilities by sharing expertise and mentoring junior engineers. Directly contribute to Synopsys reputation for excellence in silicon design and verification solutions. Drive innovation in verification methodologies, raising the bar for future projects and industry standards. Improve customer satisfaction by providing expert support and resolving technical challenges efficiently. Facilitate cross-functional collaboration, fostering a culture of knowledge sharing and continuous learning. What Youll Need: 8-15+ years of hands-on experience in ASIC digital verification, preferably in a lead or staff engineering capacity. Proficiency in Verilog, VHDL, and/or SystemVerilog languages, with a strong grasp of modern verification methodologies such as UVM. Experience in developing and debugging verification environments, including test planning, simulation, and coverage analysis. Familiarity with industry-standard scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization. Excellent written and spoken English communication skills, with the ability to document and present technical concepts clearly. Strong organizational skills, with experience managing multiple priorities and delivering high-quality results under tight deadlines. Who You Are: Innovative and proactive, with a passion for continuous learning and embracing new technologies. Collaborative team player who thrives in a diverse, multicultural environment. Analytical thinker with exceptional problem-solving and troubleshooting abilities. Effective mentor and leader, capable of guiding and inspiring junior engineers. Detail-oriented and process-driven, committed to delivering excellence in every project. Resilient and adaptable, able to multitask and manage shifting priorities in a fast-paced setting. The Team Youll Be A Part Of: You will join a world-class team of verification engineers dedicated to delivering high-performance, reliable ASIC solutions. Our team values technical excellence, innovation, and collaboration. We work closely with architects, designers, and validation teams to ensure robust product delivery. As a senior member of the team, you will have the opportunity to influence verification strategies, lead technical initiatives, and mentor the next generation of engineering talent at Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less