1570 Tcl Jobs - Page 7

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications I) Position Summary Key Objective / Purpose of the Job: The key objective of the position is to provision IP/ MPLS based services on Tata Communication Global Enterprise network. The position will serve as the Technical Authority assisting in deriving implementation guidelines for the Projects. In addition to provisioning new services, the position is also responsible for performing migrations and change managements on the existing customer circuits during critical planned events and downtimes. The incumbent will also act as SPOC for the Project and scopes defined. Also handles the escalations for 24x7 shift. Major Activities Provision IP/ MPLS based services on Tata Communication Global Enterprise network. The position is also responsible for testing the configured customer services L3 VPN/ L2 VPN/ Internet to the deliverable parameters (SLA) before handing them to Service Assurance teams. The position requires coordinating with various teams for provisioning related issues and resolving the same. Act as SPOC for the Projects and scopes defined for implementation derivations and task planning. Escalation support for 24x7 shift activities along with technical discussion. Provide assistance to team members by way of assisting them in resolving challenging technical problems, sharing knowledge and adhering to quality processes in ensuring objectives are met. The above-mentioned configuration and testing of services to be done on primarily on Alcatel and Juniper devices. Performing migrations and change managements on the existing customer circuits during critical planned events/ downtimes and ensuring the activity completion in stipulated time frames. Provisioning of customers on various NNIs (L2 and L3 NNIs). Provisioning of AWS, IZO, Google, and Cloud Computing Services on TCL MPLS platform. II) Person Specification Essential Qualifications: Candidate must possess at least a Bachelor of Engineering/Technology (Telecommunication/ Computers) or equivalent degree with min. 7 years of work experience. Requisite Skills: Technical Telecom Experience. Sound knowledge of products and services. Sound knowledge of IP/MPLS and MPLS based VPNs. Excellent knowledge of Network Fundamentals, Routing protocols ( OSPF, BGP), Switching (VTP,STP,MSTP) and advanced protocols(LDP,MPLS) and QoS and Multicast. Configuration and troubleshooting skills on Nokia (Alcatel), Cisco and Juniper routers is a must. Functional Problem-Solving abilities will help stay on top of issues besides helping in resolving the same smoothly & efficiently. Good Interpersonal skills matters. Systems and process knowledge are key drivers on the job. Behavioral Systematic approach towards work areas. Good analytical skills Ability to work in team Should be able to cope up excellently under stressful circumstances. Good communication skills Work Experience Should have worked in a service provider’s environment where network device configuration and maintenance would have been a Core activity. Familiarity with Cisco and Juniper equipment’s and configurations is must. Exposure to IP/MPLS and MPLS based VPNs is mandatory. Certifications: CCIP/ CCNP. CCIE would be an added advantage. 5-6 years’ experience in Networking field.

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications Job Description The role is responsible for support pricing initiatives for Enterprise Voice Services portfolio, including International Outbound, ITFS, LNS, Cloud Voice, and Domestic Voice Services and others. This would involve understanding of customers commercial expectations, understanding of TCL Voice & Application product offering & solution proposed and developing a Win-Win commercial propositions. Other responsibility part of the role such as developing pricing models, managing large-scale RFPs, ensuring account profitability, conducting margin analysis, and performing cost benchmarking to maintain competitive positioning. Responsibilities Lead and drive team to provide support to sales teams for commercial analysis and deal preparation through interfacing with product and sales teams to ensure providing efficient and timely support for deals. Provide support on bid proposal creation and submission. Work is performed with minimal direction and reviewed by senior management. Provides resolutions to a diverse range of complex problems Pricing Strategy & Modeling - Develop and maintain dynamic pricing models for various voice services. Analyze market trends, cost structures, and competitor pricing to inform pricing decisions. Collaborate with finance and product teams to align pricing with business objectives. RFP Management - Lead pricing responses for large and complex RFPs. Work closely with sales, legal, and technical teams to ensure competitive and compliant proposals. Evaluate pricing scenarios and provide recommendations to maximize win rates and profitability. Profitability & Margin Analysis - Monitor and manage profitability across accounts and services. Conduct regular margin analysis to identify opportunities for improvement. Implement pricing adjustments based on performance metrics and market dynamics. Cost Benchmarking - Perform cost benchmarking across regions and services to ensure cost competitiveness. Maintain a database of cost inputs and vendor pricing for reference and analysis. Support strategic sourcing and vendor negotiations with pricing insights. Stakeholder Collaboration - Partner with sales, finance, product, and operations teams to support pricing decisions. Provide training and guidance on pricing tools and methodologies. Minimum Qualification & Experience Experience in finanace & product management preferred. Desired Skill sets Experience in commercial operations Intermediate experience in managing elements of the product management lifecycle Financial & business acumen, knowledge of the industry Analytical skills & strategic acumen Strong presentation & communication skills Proficiency in using MS Excel, MS word, Power-point Experience in developing complex pricing models and pricing strategies. Conversant with financial accounting practices, such as taxation, balance sheet and overhead treatments.

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications Job Description Responsible for the planning and design of wireline transmission Core/Agg & Access IP-MPLS Network architecture. This includes- designing the network architecture, technology planning, network planning across multiple layers, build network assets involving concept planning, procurement & overseeing implementation with the objective of designing and implementing optimum network solutions to meet the needs of the customer. This role contributes in defining the direction of the plans based on the business strategy, with a significant mid-term impact on business unit overall results.The role also includes evaluation of new technology and product suitable for deployment as per business requirement including high level & low level designs. Responsibilities Manage the enhancement of existing or new development of network architecture and components by understanding needs, evaluating impact, solution designing, overseeing testing, and facilitating roll out of solutions. Designing of Wireline transmission based network architecture Review and submit Technology strategy papers related to emerging platform technologies. Create customized solution as per market requirement Define resolution mechanism to prevent recurrence of escalations. Support evaluation of different technology in market as a part of RFI/RFP process Technical evaluation of new technology/device/card by testing it in TCL/Vendor lab Define network maintenance processes and procedures and monitor maintenance activities ensuring effective coordination with relevant teams. Assess the new requirements in terms of capacity, technology configuration required, performance enhancements, CAPEX required etc. Perform Proof of Concept testing in network Support for API based integration of new devices and services in IT systems Plan for capacity augmentation in network as per market requirement and growth projections Provide support to project implementation team as a technical expert by providing high level and low level design documents Monitor and Analyze Key Performance Indicators of network Support Operations and Maintenance teams by designing resiliency for network as per the analysis of KPIs Publish Weekly/Monthly/Quarterly KPI, Capacity reports Proactively plan and support for migration of legacy devices to new platforms Desired Skill sets Strong technical skills-IP routing protocols (BGP/ISIS, MPLS, OSPF) and switching (ERPS) and L2VPN/L3 VPN, ELINE/ETREE/ELAN services Experience in IP Network planning, designing, building, and implementing Network platform projects. Hands on experience in IP Network deployment in Telco Environment Hands on experience in legacy platform migrations and network optimization projects Knowledge of new and upcoming network platform technologies including Segment Routing and EVPN CCNA ,CCNP certifications will be an added advantage

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications Job Description The role is responsible for commercial modelling and (or) bid management process of large and complex opportunities for a region. The role owns the commercial/financial build of major sales opportunities in the region. This would involve understanding of customer s commercial expectations, understanding of TCL product offering & solution proposed and developing a Win-Win commercial propositions. The role also facilitates effective bid qualification and is responsible for obtaining all necessary authorization for the successful completion of the bid. This is a tactical role with a significant mid-term impact on business unit overall results. Responsibilities Facilitate contract negotiations with legal, sales, commercial manager, and the customer, as needed. Reviewing key proposal from commercial governance perspective and advising sales team on deviations Manage the production of customer proposals, ensuring a win strategy is developed and executed to produce proposals and contain a compelling proposition to the customer, presentation of our solution and the value it brings to our customers. Initiate corrective action where necessary by forward planning and forecasting, to ensure optimum utilization of company resources and promote customer satisfaction. Manage high value financial contracts and assess changes potentially impacting the underlying business case. Awareness of commercial and legal risks and consequences. Facilitate effective bid qualification and obtain all necessary authorization for the successful completion of the bid. Working with sales teams to assist in bid / no bid decisions, bid strategies and partnering decisions. Own and maintain the bid risk register and the development of the mitigation strategies required. Flag any issues or risks to the appropriate resources within the business. The role may be an individual contributor or may lead a small team. Minimum Qualification & Experience experience in Finance preferred Desired Skill sets Experience in commercial operations or bid management roles Financial & business acumen, knowledge of the industry Analytical skills & strategic acumen Strong presentation & communication skills Proficiency in using MS Excel Ability to work with complex data sets. Highly analytical role that requires techno-commercial acumen Experience in developing complex pricing models and pricing strategies. Financial forecasting Conversant with financial accounting practices, such as taxation, balance sheet and overhead treatments.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Work with the team on Verilog RTL and scripted flow implementation of the specified Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design. Work with the team on Verilog testbench implementation of the specified verification tests for DFT features and use case. Work with the team on automation scripts intended for robustness of implementation quality and improvement of efficiency. Minimum Qualifications: Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 2 to 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Preferred Qualifications: VLSI circuit physical behaviors in silicon (electrical migration, temperature/voltage variation effects). Basic timing concepts, including setup and hold, metastability. Some EDA tools usage experience Strong verbal communication skills and ability to thrive in a dynamic environment Scripting/coding language: Tcl, Python, Perl, or c/c++. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

Job Title: RTL Design Engineer Experience: 3–5 Years Company: eInfochips (An Arrow Electronics Company) Location: Ahmedabad/ Noida Job Type: Full-Time Job Description: eInfochips is looking for talented RTL Design Engineers with 3–5 years of experience in digital design. You will be working on IP and SoC-level RTL development for leading semiconductor clients across domains like Automotive, Consumer, Industrial, and AI. Key Responsibilities: RTL design using Verilog/SystemVerilog for IP and SoC subsystems Perform synthesis, linting, CDC/RDC analysis Interface with verification, physical design, and architecture teams Support SoC integration and debug Ensure design quality and timing closure Required Skills: 2+ years of hands-on RTL design experience Strong in digital design concepts (FSMs, pipelining, FIFOs) Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS Experience with standard protocols (AXI, AHB, APB) Basic scripting skills (TCL, Perl, Python) How to Apply: 📩 Send your resume to: Nshalini.singh@einfochips.com

As a Principal Physical Design Engineer (CAD) at Ampere, you will be part of a dynamic Processor Design group pioneering the realm of high-performance implementation and physical design. Your role will involve developing and maintaining physical design flows for cutting-edge designs that push the boundaries of technology. Your responsibilities will include collaborating closely with the implementation and physical design team, addressing flow issues through debugging, evaluating the impact of technology changes on area, power, and timing by running test designs, and automating new flow practices to enhance design efficiency. To excel in this role, you should hold an M.Tech in Electronics Engineering or Computer Engineering with a minimum of 6 years of semiconductor experience, or a B.Tech in the same field with at least 8 years of relevant experience. You should have a strong background in physical design CAD flow encompassing synthesis, place & route, and floor planning, and it would be advantageous to have experience in power distribution, static timing analysis, and physical design verification. Your expertise should extend to hierarchical P&R and flow development, with proficiency in floorplanning, power distribution, pad ring construction, placement, clock tree synthesis, and routing. Proficiency in scripting languages like TCL, Perl, and Makefile is crucial, along with a knack for developing intricate algorithms and managing P&R flows effectively. Furthermore, familiarity with chip-finishing aspects such as metal fill, spare cells, DFM rules, and boundary cells for the latest process technologies is desirable. Adept communication skills and problem-solving abilities will be key in your success in this role. At Ampere, we offer a competitive benefits package that includes premium medical, dental, and vision insurance, parental benefits, retirement plans, and generous paid time off to support your well-being and work-life balance. Our inclusive culture encourages employees to innovate, grow, and contribute to sustainable future designs. Join us at Ampere to be a part of a team that is shaping the future of computing and cloud technology. #LI-SF1,

JOB NAME : AMS Verification Engineer (Mandatory to have AMS verification with UVM test : As per market : Hyderabad Please Note : it will be virtual interview, WFO initially later depends on the project and project manager, General Description : The position involves design verification of next generation IPs /SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate Will Require Close Interactions With Design, SoC , Validation, Synthesis PD Teams For Design Convergence. Candidate Must Be Able To Take Ownership Of IP/Block/SS To work in AMS Verification domain with UVM test batch relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Experience working on AMS Verification on multiple SOCs or sub-systems. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites. Developing and validating high-performance behavior models. Verifying of block-level and chip-level functionality and performance. Team player with good communication skills and previous experience in delivering solutions for a multi-national client. Tool suites : Predominantly analog (Cadence Virtuoso). SPICE simulator experience. Fluent with Cadence-based flowCreate schematics, Simulator/Netlist options etc.. Ability to extract simulation results, capture in a document and present to the team for peer review. Supporting silicon evaluation and comparing measurement results with simulations. UVM and assertion knowledge would be an Level : 8-12 years in Industry(3+yrs Requirements : Bachelor or Masters degree in Electrical and/or Computer Qualifications : Proficient in at least one of the following languages : Verilog, System Verilog, Verilog AMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Qualifications : Mentoring skills. Exceptional problem-solving skills. Good written and oral communication Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs). Employee Stock Purchase Plan (ESPP). Insurance plans with Outpatient cover. National Pension Scheme (NPS). Flexible work policy. Childcare support. (ref:hirist.tech)

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

As a qualified candidate for this role, you should possess a Bachelor's degree in Electrical Engineering or a related field, or demonstrate equivalent practical experience. Additionally, you should have at least 3 years of hands-on experience with Front-End CAD tools and a proven track record of writing production scripts using languages such as Python or TCL. Ideally, you would hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. It would be advantageous to have a deep understanding of Institute of Electrical and Electronics Engineers (IEEE) Unified Power Format (UPF) standards, as well as knowledge in Machine Learning (ML) based acceleration and Register-Transfer Level (RTL) concepts including connectivity, feedthroughs, re-partitioning, UPF, and Local Enhanced Content (LEC). Joining our team means being part of a collective effort to innovate and create custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in shaping cutting-edge hardware experiences that are enjoyed by millions globally. At Google, we strive to organize the world's information and make it universally accessible and useful by leveraging the synergy of AI, Software, and Hardware technologies. In this role, your responsibilities will include developing methodologies for various front-end tasks, collaborating closely with front-end teams to address requirements effectively, coordinating with cross-functional domains to facilitate the development and deployment of Computer Aided Design (CAD) solutions, advocating for enhancements from electronic design automation (EDA) vendors to cater to Google's custom needs, and partnering with EDA and verification teams to pioneer new industry solutions.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

As a DFT Engineer at Google, you will play a key role in developing custom silicon solutions for Google's direct-to-consumer products. Your expertise in DFT methodologies and Electronic Design Automation (EDA) tools like Tessent will contribute to the innovation and performance of products used by millions worldwide. Working closely with RTL and Physical Designer Engineers, you will help shape the next generation of hardware experiences. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage and power domains. You will also be involved in writing basic scripts to automate the DFT flow and developing tests for production in the Automatic Test Equipment (ATE) flow. To be successful in this role, you should have a Bachelor's degree in Electrical or Electronics Engineering, along with at least 3 years of experience in DFT methodologies. Experience in areas such as ATPG, Low Power designs, BIST, JTAG, and IJTAG tools and flow will be beneficial. Preferred qualifications include experience in architecting/developing DFT flows and methodologies, as well as collaborating with Design, Physical Design (PD), and Static Timing Analysis (STA) teams. Strong scripting skills in languages like Python and TCL are also desired. Join us in our mission to organize the world's information and create helpful experiences for users through innovative hardware technologies. Your contributions will play a vital role in making people's lives better through technology.,

As a member of the methodology team in the Design Engineering category based in Bengaluru, India, your primary responsibility will be to lead the development, enhancement, and deployment of low-power structural check methodologies for multiple SoC and IP projects. Your role will involve creating automated flows to ensure UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. Collaboration with design, verification, and EDA partners will be essential to establish robust, scalable, and high-coverage power-aware design signoff strategies across different technology nodes and product segments. Your key responsibilities will include developing and maintaining low-power structural check methodologies, building automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP, ensuring power intent consistency, integrating structural checks into signoff regressions, and collaborating with vendors and internal teams to enhance tools and drive global adoption. You will also be involved in audits, quality reviews, and milestone checks to maintain the quality of the methodologies. To excel in this role, you should possess at least 5 years of experience in low-power structural methodologies and UPF/CPF-based flows. A deep understanding of power intent specs, domain partitioning, isolation, and retention is crucial, along with hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP. Proficiency in scripting (Python, Perl, TCL) for flow automation, experience with large SoC/IP designs, and strong communication and documentation skills are also required. Nice to have skills and experience include familiarity with formal verification or functional simulation for power-aware designs, knowledge of complex power analysis, exposure to hierarchical low-power signoff strategies, and involvement in industry working groups or technical conferences. Additionally, experience with power-aware DFT, scan strategies, and low-power aware synthesis flows will be advantageous. At Arm, we value behaviors such as partnership, dedication, collaboration, communication, originality, resourcefulness, team and personal development, impact, and influence. If you require any accommodations during the recruitment process, please reach out to accommodations@arm.com. We believe in equal opportunities and offer a hybrid working environment that promotes flexibility and personal wellbeing. Join us in shaping extraordinary teams and making a difference in the world of technology.,

Our Purpose Mastercard powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title And Summary Senior Software Engineer Overview This contractor position is on Mastercard’s performance engineering team working closely with the other Authorization development teams. You will have the chance to use and improve a suite of tools to assess transaction time each release. We are looking for engineers that are passionate about performance and development with a constant focus on improving quality. All About You Have you created many scripts to automate and interface with programs (i.e. shell script, TCL, Perl, Python)? Do you understand throughput, latency, memory, and CPU utilization? Have you spent significant time in Linux environments with some experience administrating? Have you developed software before – preferably in C/C++? Do you know about different inter-process communications (i.e. shared memory, MQ, Kafka)? Do you have experience and prefer working in an Agile environment? Have you worked with big, real-time, and distributed systems? Design, configure, and execute performance tests Work closely with software development teams to identify risks and anticipate problems to ensure that each release does not negatively impact performance Improve the current performance environment with your own code, automation, and onboarding of external tools (i.e. Dynatrace and Splunk) Drive performance issues to resolution Corporate Security Responsibility All Activities Involving Access To Mastercard Assets, Information, And Networks Comes With An Inherent Risk To The Organization And, Therefore, It Is Expected That Every Person Working For, Or On Behalf Of, Mastercard Is Responsible For Information Security And Must: Abide by Mastercard’s security policies and practices; Ensure the confidentiality and integrity of the information being accessed; Report any suspected information security violation or breach, and Complete all periodic mandatory security trainings in accordance with Mastercard’s guidelines. R-252723

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-7 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python , and/or TCL

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Firmware Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Experience with C/C++ Experience with software development in a Linux environment Experience in low level driver development, register interface programming, general algorithms. Experience in Firmware development using FreeRTOS or Zephyr is an added advantage. Experience with embedded processors such as ARM, RISC Experience with industrial standard devices e.g. Ethernet, PCIe, SPI, I2C, USB, GPIO and Memory architectures DDR/SDRAM/DMA Experience in high performance and low latency, multi-threaded, high throughput SRIOV-capable PCIe-subsystem drivers for compute and network acceleration Scripting language experience like Perl, Python or TCL is an advantage Excellent interpersonal, written and verbal communication skills A self-starter and team player TekWissen Group is an equal opportunity employer supporting workforce diversity.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience – 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-systems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control systems like Mercurial(Hg), Git or SVN

Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.