1570 Tcl Jobs - Page 5

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements RequiredBachelor's, Electrical Engineering or equivalent experiencePreferredMaster's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience - 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /masters degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Principal Design Verification Engineer Job Overview MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs. Key Responsibilities Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure. Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications. Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis. Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors. Employ formal verification techniques to augment random verification and ensure exhaustive coverage. Analyze verification coverage metrics to identify and close coverage gaps efficiently. Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell. Mentor junior verification engineers, providing technical guidance and leadership within the verification team. Qualifications Master`s degree or higher in Electronics, Electrical, Computer Engineering. 15+ years of relevant verification experience, specifically in CPU or complex SoC verification. Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks. Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification. Proficiency in SystemVerilog, Verilog, C, C++, and Assembly. Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI. Strong scripting skills in Python, Perl, TCL, or Shell. Experience with CPU architectures, particularly RISC-V, ARM, or MIPS. Preferred Experience Experience with RISC-V architecture. Familiarity with functional safety standards (e.g., ISO 26262). Prior exposure to FPGA prototyping and emulation platforms. What MIPS Offers Opportunity to be part of a dynamic team creating industry-leading RISC-V processors. Autonomy with extensive support from industry experts. Opportunities for significant career growth and technical advancement. Competitive compensation and comprehensive benefits package About MIPS MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC, Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy, Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules, Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level, Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development, Senior engineers are also encouraged to support junior members, Required Skills And Experience 4-10 years of proven experience in working on IP/Subsystem/Soc Verification Experienced in Protocol on Flash Storage device Controller with unipro and MIPI PHY, Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs, Good Skills in System Verilog, shell programming/scripting (e-g Tcl, Perl, Python etc ) Experienced in one or more of various verification methodologies UVM, formal and low power, Exposure to all stages of verification requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support, Experience with various front-end verification tools Dynamic simulation tools, Static Simulation tools and Debuggers, Nice To Have Skills And Experience Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture / micro-architectures

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications The Company A part of the Tata Group, Tata Communications is a global digital ecosystem enabler powering today’s fast-growing digital economy in more than 190 countries and territories. Leading with trust, it enables digital transformation of enterprises globally with collaboration and connected solutions, core and next gen connectivity, cloud hosting and security solutions and media services. 300 of the Fortune 500 companies are its customers and the company connects businesses to 80% of the world’s cloud giants. The Opportunity We are living in an era where technology is not just enhancing livelihoods but also fundamentally transforming businesses, communities, and lives globally. Tata Communications has been at the forefront of this movement — accelerating digital transformation for clients across the world, driving innovative business models, and enabling competitive advantages through resilience and collaboration. We’re on a mission to hire the best and are committed to be an equal opportunity organisation. We realize that new ideas can come from anywhere in the organization, and we know the next big idea could be yours! If you're ready to join a dynamic, forward-thinking team and make a tangible impact on our brand’s future, this is your chance! We’re looking for a highly analytical, creative, and passionate brand manager who can work across geographies to be a part of the brand team. Designated as Deputy General Manager – Brand Marketing (Global Marketing) Located in India Reports to Chief of Brand What You’ll Do Be the Brand Champion: Define & Evolve: Take charge of developing and refining our brand's voice and positioning. Ensure it resonates with our stakeholders across customers, analysts, shareholders. Building, managing, and externally positioning brand communications strategies in partnership with the overall TCL Communications team and brand marketing function. Drive thought leadership and content development to advance brand narrative and awareness among key audiences and across geographies. Ensure brand's image, messaging, and positioning are consistent and effectively communicated across social media platforms. Oversee social media strategy, content creation, engagement, and analysis to build and maintain a strong brand presence online. Campaign Build: Lead the creation of compelling and innovative marketing campaigns that elevate our brand across all touchpoints—whether it’s digital, print, or experiential marketing. Customer Insights: Dive deep into consumer behaviour and market trends to guide and shape marketing strategies. Your understanding of the customer will drive everything we do. Drive Growth & Performance Impactful Strategy: Develop customer insight drives campaigns to build a compelling and relevant campaign ROI Focused: Manage the marketing budget effectively, ensuring that every campaign maximizes ROI while staying true to brand values. Brand track Survey: Gather data through various track surveys to monitor brand health, track brand awareness, and make informed decisions about brand strategy & marketing campaigns. Collaborate & Lead Multi agency liaison and internal stakeholder engagement are par for the course. Who We’re Looking For You’re a Strategic Thinker: You thrive in creating long-term, big-picture strategies while also executing with precision. You have the ability to analyse data and turn it into actionable insights that drive brand growth. You’re Creative & Curious Innovation is at your core. You’re always looking for ways to make the brand fresh, exciting, and relevant. You are not afraid to challenge the status quo and bring bold ideas to the table. You’ve Got Experience Bachelor’s degree or equivalent experience in brand building, public relations, communications, journalism, brand consulting or marketing or related field 10+ years of communications experience working to develop, build, and grow overall brand presence and narrative. Exceptional writing/editing and storytelling skills. Strong media strategy skills. Consistent track record of successfully building brands across B2B brands Broad business understanding, strong analytical abilities and critical, creative problem solver. Experience managing cross-functional or cross-team projects Experience in developing and leading high impact social and content strategies and engaging communities. Drive and deliver outsized campaigns and engagements for key launch moments that activate the early adopter and developer community in a social-first way. You’re a Strong Communicator Your storytelling skills are unmatched—whether you're presenting to senior leadership or working with cross-functional teams, your communication is clear, engaging, and persuasive and rooted in insights What We Offer A global opportunity to work on a brand with deep global associations like Formula One A challenge that enables you to work with multi-cultural teams and a global management team Tata Communications is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. Ready to Make Your Mark? If you’re a passionate, driven, and innovative Brand Manager looking to grow your career and take on exciting challenges, we want to hear from you.

About Scaledge: Scaledge is one of the fastest growing product engineering services companies focused on Semiconductor Chip - Design & Verification, Processors, System design and related Embedded Software development for domains like Storage, RISC-V, AI/ML, Automotive, Consumer, Networking and IoT. We are headquartered in Silicon Valley, USA with multiple design centers across India, UK and Canada. Scaledge has a strong history of technology, methodology & domain expertise in IP/ASIC/SOC verification in Storage, Networking, Mobile & Consumer industry About Opportunity: Scaledge is looking for experienced, talented Verification Engineers (ASIC/IP/SOC/CPU/GLS) for dynamic and innovative Team. As a member of the team, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies Requirements Experience 5+ years. Hiring for Senior Engineer, Technical Lead, and Architect levels Dedicated/hands-on ASIC/IP/SOC DV experience. Experience working on block level UVM test benches - writing drivers, scoreboards, sequences, constraints, and functional coverage models Strong interest in understanding the architectural and micro-architectural details of a design. Strong interest in debugging complex issues Drive and adopt new verification methodologies to improve effectiveness and efficiency Experience working on the memory subsystem is a plus Responsibilities Build UVM test benches and own the verification of an IP from start to finish. Create coverage driven verification plans from specifications. Execute, review and refine to achieve coverage targets. Set up regressions and triage failures. Debug and drive any design and verification bugs found, to closure. Work with the team to improve DV methodology and infrastructure. Required Skills Strong knowledge of Verilog, System Verilog, and Object-Oriented Programming Experience with modern verification techniques, especially including System Verilog, UVM, constraint-random and functional coverage methodologies Complete understanding of verification life cycle and ability to create of comprehensive verification plans Knowledge of high-speed PCIe, DDR, USB, AXI, APB, AHB protocols Experience verifying networking protocols such as Ethernet is a plus Experience with scripting languages such as Python, Tcl, or Perl Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Strong technical writing and verbal communication skills Education BTech/MTech in Electronic/Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience.

Company Description MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with a global presence in Silicon Valley, USA, and India, employing over 1300 engineers. The company offers comprehensive engineering solutions that include silicon design, verification, systems, software, and device engineering, AI/ML solutions, and test automation services. With a strong track record of shipping millions of connectivity ICs and achieving first-time right silicon for over 200+ SoC tape-outs, MosChip® is a reliable partner in the semiconductor industry. Role Description This full-time role is for a Senior Lead STA Engineer specializing in Synthesis, LEC, and CLP. The role is on-site and located in Hyderabad. Daily responsibilities include performing static timing analysis, developing and implementing design constraints, synthesis and timing closure for complex designs, working on logic equivalence checking, and collaborating with cross-functional teams to ensure efficient design implementation and verification processes. Qualifications Expertise in Static Timing Analysis (STA), Synthesis, LEC (Logical Equivalence Checking), and CLP (Clock Power Reduction) Experience with EDA tools such as Synopsys PrimeTime, CADENCE Tempus Proficiency in scripting languages like Perl, TCL, and Shell Strong understanding of digital design fundamentals and VLSI design flow Experience with backend design processes including Physical Design and Signoff flows Excellent communication and teamwork skills Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field Over 5+ years of relevant industry experience is preferred

Job Description We are seeking skilled engineers to join our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus. Roles & Responsibilities Develop and execute RTL test benches using VCS/SystemVerilog/UVM Perform functional and gate-level simulation, debug with Verdi Run DFT pattern simulations, scan insertion validations Conduct Static Timing Analysis (STA) with PrimeTime Execute power-aware and multi-mode multi-corner (MMMC) simulations Validate interfaces considering IC package parasitic (SiP/2.5D/3D-IC understanding is a plus) Collaborate with teams to correlate package- and board-level effects with chip-level behavior Analyze analog layout impact on mixed-signal simulation accuracy (awareness of layout parasitic) Requirements Strong hands-on experience with Synopsys tools: VCS (RTL simulation), Verdi (debug), PrimeTime (timing), TetraMAX/TestMAX (DFT), HSPICE/FineSim (analog simulation exposure is a plus) Familiarity with IC packaging technologies, chip-package co-simulation, and signal/power integrity considerations Understanding of analog layout practices and their influence on simulation/verification Strong scripting skills (TCL, Perl, Python) for automation Excellent debugging, documentation, and communication skills Preferred Qualifications Bachelor’s or Master’s in Electronics, VLSI, or Electrical Engineering & 5-8 Years of Relevant Experience is mandatory Awareness of multi-die, chip let, or 3D IC architectures Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS) Strong analytical and collaborative mindset Master in VLSI / Microelectronics Benefits Challenging job within a young and dynamic team. Performance-driven, Career Progression Opportunities. Attractive remuneration package: On par with Industry Standards. Opportunity to join an organization experiencing year on year growth. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#6875E2;border-color:#6875E2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered="">

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished analog IC design engineer with a proven track record of delivering high-performance, high-speed circuits in advanced technology nodes. With over a decade of hands-on experience, you possess deep technical expertise in transistor-level circuit design, particularly in FinFET and cutting-edge process nodes. You thrive in fast-paced, collaborative environments and enjoy working on challenging projects that push the boundaries of what’s possible in analog and mixed-signal design. Your passion for innovation is matched by a meticulous attention to detail and a strong commitment to quality. You are comfortable navigating complex SerDes architectures, from initial concept through to silicon validation, and you approach problem-solving with creativity and a data-driven mindset. You value teamwork and diversity, and you communicate your ideas clearly to colleagues from a variety of backgrounds, including digital designers, CAD engineers, and customers. What You’ll Be Doing: Review and interpret SerDes standards to develop innovative transceiver architectures and detailed sub-block specifications. Investigate, propose, and design novel circuit architectures that overcome performance bottlenecks, achieving significant improvements in power, area, and speed. Collaborate with cross-functional teams to streamline design and verification methodologies, ensuring efficiency and design quality. Oversee physical layout processes, minimizing the impact of parasitics, device stress, and process variation for optimal silicon performance. Present and review simulation results within the team and externally at industry panels or customer reviews, articulating complex technical concepts clearly. Document design features, methodologies, and test plans to ensure knowledge transfer and reproducibility. Consult on electrical characterization of SerDes IP, analyze customer silicon data, and propose solutions for post-silicon enhancements. The Impact You Will Have: Drive innovation in high-speed analog and mixed-signal design, directly contributing to Synopsys’ leadership in SERDES IP. Enable customers to achieve cutting-edge performance, power, and area metrics in their next-generation silicon products. Advance the adoption of the latest FinFET and gate-all-around technologies through robust, reliable analog solutions. Raise the bar for design quality and efficiency by introducing best practices in architecture, verification, and layout. Mentor and inspire a diverse team of engineers, fostering a culture of learning and continuous improvement. Strengthen Synopsys’ reputation by representing the company at industry events and delivering high-impact technical presentations. What You’ll Need: MTech/MS (4+ years) or BTech/BS (5+ years) in Electrical Engineering, Computer Engineering, or related field. Extensive analog IC design experience, especially with FinFET technologies and advanced process nodes. Expertise in transistor-level CMOS design, including successful CMOS tape-outs. Deep understanding of high-speed designs (Multi-Gbps), especially PAM4 SerDes architectures and sub-circuits (TX, RX, equalizers, PLL, DLL, regulators, oscillators, ADC/DAC). Proficiency with analog/digital interaction techniques for circuit optimization, calibration, and adaptation. Familiarity with ESD, custom digital design, design for reliability, layout effects, and signal integrity issues. Hands-on experience with schematic entry, physical layout, design verification tools, and SPICE simulation. Knowledge of scripting languages (TCL, PERL, MATLAB) for simulation post-processing. Excellent communication and documentation skills. Who You Are: An analytical thinker with a passion for solving complex technical challenges. A collaborative team player who values input from diverse perspectives. An effective communicator, able to convey technical details to both experts and non-experts. Detail-oriented, organized, and committed to quality and continuous improvement. Adaptable to changing priorities and eager to learn new technologies. Proactive in mentoring and supporting the professional growth of others. The Team You’ll Be A Part Of: You’ll join a world-class analog and mixed-signal R&D team based in Hyderabad, focused on developing high-speed SERDES IP for the latest process technologies. Our team brings together experts in analog, digital, and CAD, fostering an environment of innovation, knowledge sharing, and technical excellence. We work closely with global teams and customers to deliver industry-leading solutions that shape the future of connectivity. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: Verification Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and highly experienced engineering professional, passionate about verification and digital design methodologies. With at least 15 years of solid experience in IP and SoC verification, you have consistently demonstrated technical excellence and leadership in your career. You thrive in challenging environments and are adept at architecting robust verification infrastructures from the ground up, particularly within the EDA ecosystem. You possess deep hands-on knowledge of industry-leading tools such as Synopsys VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Your expertise enables you to design unified reference flows and scalable methodologies that empower teams and accelerate project success. You excel at independently owning and delivering on complex assignments, while also being a collaborative team player who enjoys mentoring and elevating junior engineers. Your communication skills are outstanding, allowing you to articulate technical concepts to diverse audiences and influence cross-functional teams. You have a proven ability to multi-task, manage priorities, and drive technical initiatives with a strategic mindset. Your academic foundation includes a bachelor’s degree in electronics, electrical, or computer engineering, and you continuously seek to expand your knowledge and impact in the field of digital IP verification. You are ready to take on a leadership role, shaping methodology and best practices for the next generation of high-performance silicon designs. What You’ll Be Doing: Architecting and implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects. Partnering with global engineering teams to define, document, and propagate best-in-class verification methodologies and standards. Leading and mentoring junior engineers, fostering a culture of technical growth, innovation, and collaboration within the team. Driving technical initiatives and independently managing high-impact assignments, ensuring timely and high-quality deliverables. Collaborating closely with tool development teams to influence product evolution and optimize verification workflows for maximum efficiency. Supporting customers and internal stakeholders by troubleshooting, optimizing, and refining verification processes and flows. The Impact You Will Have: Elevate Synopsys’ digital IP verification capabilities by delivering robust, unified, and scalable methodology solutions. Accelerate time-to-market for high-performance silicon products by streamlining and standardizing verification processes. Empower global verification teams with best-in-class flows, tools, and practices, driving consistent project success. Shape the verification strategy for next-generation Synopsys IP and SoC offerings, directly influencing product quality and customer satisfaction. Mentor and develop the next wave of verification engineers, fostering a culture of learning and technical excellence. Contribute to the evolution of Synopsys’ EDA tool ecosystem by providing critical feedback and championing innovative solutions. Enhance Synopsys’ leadership position in the semiconductor industry through continuous improvement and adoption of cutting-edge verification methodologies. What You’ll Need: Minimum 15 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership. Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. Demonstrated ability to architect and implement verification flows and infrastructure for complex digital designs. Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages). Bachelor’s degree in electronics, electrical, or computer engineering (advanced degrees a plus). Experience with multi-tasking and managing technical projects independently. Ability to document, communicate, and propagate technical methodologies across global teams. Who You Are: Innovative problem solver who thrives in dynamic, fast-paced environments. Excellent communicator, able to distill complex technical topics for diverse audiences. Natural mentor and team player, passionate about knowledge-sharing and team development. Strategic thinker with a keen eye for detail and a commitment to quality. Self-motivated leader who takes initiative and drives projects to successful completion. Adaptable, resilient, and eager to learn and grow alongside industry leaders. The Team You’ll Be A Part Of: You will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Senior Executive EXL/SE/1407920 Clinical & Pharmacy ServicesNoida Posted On 27 Jul 2025 End Date 10 Sep 2025 Required Experience 1 - 3 Years Basic Section Number Of Positions 1 Band A2 Band Name Senior Executive Cost Code D900010 Campus/Non Campus NON CAMPUS Employment Type Permanent Requisition Type Backfill Max CTC 300000.0000 - 800000.0000 Complexity Level Not Applicable Work Type Hybrid – Working Partly From Home And Partly From Office Organisational Group Healthcare Sub Group Healthcare Organization Clinical & Pharmacy Services LOB Clinical & Pharmacy Services SBU CareRadius Country India City Noida Center Noida - Centre 59 Skills Skill DEVOPS JENKINS AZURE DOCKER DOCKER AND KUBERNETES Minimum Qualification B.TECH/B.E MCA Certification No data available Job Description Basic Function MUST have experience in Cloud AZURE and various services (Azure DevOps, AKS, ALB etc) Create Continuous Integration and Continuous Deployment Pipelines using Jenkins and Groovy Script. Technical design, coding, testing and debugging of complicated Automation Scripts in Groovy, TCL/Tk, Ruby, OR Unix Shell Scripting Hands-on experience in Ansible, Docker and Kubernetes. Adherence to the established best practices, coding standards and conventions. Knowledge of Generative AI and how we can use it in DevOps. Essential Functions Must possess Analytical thinking, with natural problem solving/finding ability Strong scripting skills to automate processes and tasks. Adhere with all policies and procedures applicable to the position, department, division and larger organization Delivery domain Working experience of Agile, Scrum and Waterfall project management methodology Working experience of creating and understanding of detailed Technical and Functional design specification. Health Care domain (Preferred) Understanding of Health Care management vertical - Knowledge of Payers, Providers, Authorization / Claims processing / Health Plan / Health Insurance / Knowledge of HIPPA / AHM Soft skills (Required) Good verbal and written communication Good analytical skills Strong Team player and mentor (depending upon the level of experience) Working Hours Working shift 12PM – 10pm IST Workflow Workflow Type Digital Solution Center

Basic Function MUST have experience in Cloud AZURE and various services (Azure DevOps, AKS, ALB etc) Create Continuous Integration and Continuous Deployment Pipelines using Jenkins and Groovy Script. Technical design, coding, testing and debugging of complicated Automation Scripts in Groovy, TCL/Tk, Ruby, OR Unix Shell Scripting Hands-on experience in Ansible, Docker and Kubernetes. Adherence to the established best practices, coding standards and conventions. Knowledge of Generative AI and how we can use it in DevOps. Essential Functions Must possess Analytical thinking, with natural problem solving/finding ability Strong scripting skills to automate processes and tasks. Adhere with all policies and procedures applicable to the position, department, division and larger organization Delivery domain Working experience of Agile, Scrum and Waterfall project management methodology Working experience of creating and understanding of detailed Technical and Functional design specification. Health Care Domain (Preferred) Understanding of Health Care management vertical - Knowledge of Payers, Providers, Authorization / Claims processing / Health Plan / Health Insurance / Knowledge of HIPPA / AHM Soft Skills (Required) Good verbal and written communication Good analytical skills Strong Team player and mentor (depending upon the level of experience) Working Hours Working shift 12PM – 10pm IST

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a minimum of 4 years of experience. Responsibilities include IR signoff for CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP, Development of PG Grid spec for different HM, and validating PG Grid and IR Drops. Additionally, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations is crucial to enhance PDN Design. The desired skill set includes hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level, proficiency in scripting languages like Tcl and Perl, and familiarity with tools such as Redhawk, Redhawk_SC, Innovus, and Fusion Compiler. The ability to communicate effectively with global cross-functional teams and experience in Power Planning/Floorplanning and Physical Verification is an added advantage. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Abiding by all applicable policies and procedures, including security requirements, is expected from Qualcomm employees. Please note that our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a CPU Integration CAD Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As part of the NUVIA team, which is now integrated into Qualcomm, you will be involved in reimagining silicon and developing computing platforms that aim to revolutionize the industry. This role offers the opportunity to collaborate with exceptionally skilled engineers to design innovative solutions that excel in performance, energy efficiency, and scalability. To qualify for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience in a related field will also be considered. The ideal candidate will have 6 to 15 years of experience with a strong academic background. As a CPU Integration CAD Engineer at Qualcomm, you will primarily focus on enabling the floor-planning, physical design, verification, and signoff of Oryon CPU cores. Your responsibilities will include collaborating with global cross-functional teams, developing and implementing flows and methodologies for various design aspects, conducting system tests, recommending improvements, and ensuring the best power, performance, and area outcomes for the silicon products. Preferred qualifications for this role include a Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science, extensive experience in high-performance chip development, proficiency in programming languages like Python and TCL, knowledge of data structures and algorithms, automation experience, familiarity with Physical Design tasks, expertise in advanced technology nodes, and proficiency with industry-standard tools such as Siemens/Mentor Calibre and Cadence Innovus. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application and hiring process. The company expects all employees to adhere to relevant policies and procedures, including those related to security and confidentiality. Staffing and recruiting agencies are advised that only individual job seekers should utilize Qualcomm's Careers Site, as unsolicited submissions will not be accepted. For further information about this exciting opportunity, please reach out to Qualcomm Careers for more details.,