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8.0 years
0 Lacs
Bengaluru
On-site
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. EDA Infrastructure Engineers are individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, EDA Infrastructure Responsibilities: Front End implementation flow development and support Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting RTL2GDS flow development and support Physical Design implementation flow development and support Minimum Qualifications: Knowledge of front-end and back-end ASIC tools and flows Experience with RTL design using SystemVerilog or other HDL 8+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support Experience with developing and supporting solutions for ASIC design environment and infrastructure Experience with communicating across functional internal teams and with vendors Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Experience setting up EDA infrastructure from scratch User experience and customer oriented solutions About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Posted 2 months ago
3.0 years
2 - 9 Lacs
Bengaluru
On-site
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.
Posted 2 months ago
2.0 years
0 Lacs
Bengaluru, Karnataka, India
On-site
Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role Familiar with Physical Design Life cycle of chip development, especially Floorplanning and PnR Hands on PD execution at block/SoC level along with PPA improvements Strong understanding of the technology and PD Flow Methodology enablement. Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them Provide tool support and issue debugging services to physical design team engineers across various sites Develop and maintain 3rd party tool integration and productivity enhancement routines Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set Strong programming experience & Proficiency in Python/Tcl/C++ Understand physical design flows using Innovus/fc/icc2 tools Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory Basic understanding of Timing/Formal verification/Physical verification/extraction are desired Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory* Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069347 Show more Show less
Posted 2 months ago
4.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071473 Show more Show less
Posted 2 months ago
1.0 - 2.0 years
0 Lacs
Hyderabad, Telangana, India
On-site
Job Description And Requirements Design, development, troubleshooting, and debugging of multi-Gb/s SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. Requirements. Looking for 1-2 years of experience in Analog design with master's degree or 2-4 years of experience in in Analog design with bachelor's degree. In depth familiarity with transistor level circuit design - sound CMOS design fundamentals Exposure to SERDES sub circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, DLL, BGR, Regulators, ADC etc) Aware of ESD issues (ie. circuit techniques, layout) Familiarity with custom digital design (ie. high speed logic paths) Knowledge of design for reliability (ie. EM, IR, aging, etc…) Knowledge of layout effects (ie. matching, reliability, proximity effects, etc…) Familiar with Custom design and/or Cadence, HSPICE, HSIM,Ultrasim,etc Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB etc…) Some knowledge of system level budgeting (ie. jitter, amplitude, noise, etc…) Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise Good communication and documentation skills. Show more Show less
Posted 2 months ago
3.0 - 6.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Digital Verification Senior Engineer, you are passionate about technology and eager to drive pre-silicon functional verification of High-Speed PHY IPs. You have a dynamic personality and a strong desire to learn and excel in pre-silicon verification activities. With a solid understanding of digital design and HDL implementation, you are ready to take on complex challenges and contribute significantly to our innovative projects. You thrive in a diverse team environment and possess excellent debug and diagnostic skills, along with proficiency in scripting and automation using TCL, PERL, or Python. What You’ll Be Doing: Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You’ll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python. Who You Are: You are a detail-oriented, analytical thinker with a strong problem-solving mindset. You possess excellent communication and collaboration skills, enabling you to work effectively within a diverse team. Your passion for technology drives you to stay updated with the latest advancements and continuously improve your skills. You are proactive, adaptable, and committed to delivering high-quality results in a fast-paced environment. The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the verification of High-Speed PHY IPs. Our team is committed to innovation and excellence, working collaboratively to ensure the highest standards of quality and performance. We value diversity and inclusivity, fostering an environment where every team member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less
Posted 2 months ago
8.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly. What You’ll Be Doing: Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence. The Impact You Will Have: Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning. What You’ll Need: A Bachelor’s degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 8 years of related experience, or a Master’s degree with 6 years of relevant experience. In-depth understanding of data structures, algorithms, and their applications. Excellent software development experience with C/C++ on UNIX/Linux platforms. Exposure to Python, TCL, and shell scripting languages is preferable. Exposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances. Demonstrated history of good analytical, debugging, and problem-solving skills. Experience with complex and large software code-based tool development. Who You Are: You are a motivated and enthusiastic engineer who excels in both independent and collaborative settings. You have a solid desire to learn and explore new technologies, and you exercise good judgment in developing methods and techniques to meet project goals. Your excellent written and oral communication skills in English enable you to collaborate effectively and present your ideas clearly. Special consideration will be given to candidates with a background in hardware functional verification and/or synthesis techniques, as well as knowledge of software specification, design processes, and regression testing. The Team You’ll Be A Part Of: You will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools. Our team is committed to pushing the boundaries of technology and delivering high-performance solutions that meet the needs of our customers. We work in a collaborative and dynamic environment, where creativity and innovation are encouraged and valued. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less
Posted 2 months ago
3.0 - 6.0 years
0 Lacs
Hyderabad, Telangana, India
On-site
Job Requirements 3 to 6 years of exp in Hands on Chip top and Block level Timing closure. Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Multimode multi corner timing knowledge and timing closure at Top and Block level. Top level timing closure with sing off STA. Top level ECO implementation strategy development for netlist, RTL and timing level changes. Scripting experience in Perl/TCL Excellent debugging skills and ability to come up with creative solutions. Technologies from 28nm and below. Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Having proficiency with either PrimeTime, Tempus and Innovus is must Work Experience Netlist and constraint sign in checks and validation. Timing constraint development at Full chip level and clean up. Performing floor-planning and routing studies and implementation at block and full-chip level Show more Show less
Posted 2 months ago
0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
Job Requirements The responsibilities will include several of the following, but not be limited to: Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Closely working with Package team and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical activities of physical design during technology readiness, design & execution In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes Work Experience Experience Range:- 4Yrs - 10 Yrs Should be able to handle PD task independently and also should be able to manage the small team Should have experience in handling >1M instance count, 1 GHz frequency designs Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Show more Show less
Posted 2 months ago
0.0 - 2.0 years
3 - 4 Lacs
Bengaluru
Work from Office
Radiant Semiconductors is a leading Semiconductor Design and Services Company with a strong presence across India and the USA. Backed by 200+ skilled engineers, over 7 years of industry relevant experience, were specialised in Design Verification, Design For Test (DFT), PD and Analog Design. We deliver tailored solutions through flexible engagement models, serving top Semiconductor Companies worldwide by our leadership team with 18+ years of expertise in product development. Role: Junior DFT Engineer Location : Bengaluru, Candidate should be flexible to work PAN India Eligibility Criteria Qualification : B.E/ B.Tech, M.Tech/M.E (Will get preference) Stream : Electronics Engineering or Related Fields Post Graduation Year : 2024 or Prior (Up to 2020) Academic Requirement : Minimum 65% throughout academics Background : Strong foundation in VLSI Design, Digital Electronics, Scan & DFT Fundamentals What we offer Competitive Salary Package aligned with Industry Standards Comprehensive Family Health Insurance Coverage Opportunity to work on high-impact semiconductor projects with top-tier global clients Professional training with the focus on industry standard EDA tools Opportunity to continuous learning and mentorship support from Industry experts Employee Recognition: Get acknowledged and rewarded for innovation, performance, and dedication Selection Process Online Registration Written Test (Shortlisted Candidates) Technical Interview (Selected Candidates) HR Discussion & Final Offer Important Dates Last Date to Application- 14th June Written test (Shortlisted Candidate )- 27th June Technical Interview (Selected Candidates)- 28th June HR Discussion & Final Offer- 28th June Click on the link to Apply now and become a part of Radiants Dynamic DFT team: https://forms.gle/ZCNcACE9Eigx5iuq6
Posted 2 months ago
2.0 - 7.0 years
8 - 11 Lacs
Bengaluru
Work from Office
Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn
Posted 2 months ago
7.0 - 12.0 years
14 - 19 Lacs
Bengaluru
Work from Office
Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *
Posted 2 months ago
1.0 - 4.0 years
2 - 5 Lacs
Bengaluru
Work from Office
Location Bangalore : Jr Devops Not Ready to Apply Join our talent pool and we'll reach out when a job fits your skills.
Posted 2 months ago
2.0 - 5.0 years
3 - 6 Lacs
Bengaluru
Work from Office
Location Bangalore : Finance & Operation Not Ready to Apply Join our talent pool and we'll reach out when a job fits your skills.
Posted 2 months ago
5.0 - 8.0 years
3 - 7 Lacs
Bengaluru
Work from Office
Location Bangalore : D365 F&O Functional Not Ready to Apply Join our talent pool and we'll reach out when a job fits your skills.
Posted 2 months ago
2.0 - 5.0 years
2 - 6 Lacs
Bengaluru
Work from Office
Location Bangalore : .NET Core Not Ready to Apply Join our talent pool and we'll reach out when a job fits your skills.
Posted 2 months ago
2.0 - 6.0 years
3 - 6 Lacs
Bengaluru
Work from Office
Location Bangalore : Mulesoft Not Ready to Apply Join our talent pool and we'll reach out when a job fits your skills.
Posted 2 months ago
3.0 - 5.0 years
7 - 11 Lacs
Bengaluru
Work from Office
At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world. Job Overview TE Connectivity's Manufacturing Engineering Teams are process leaders for stamping, molding or assembly related topics, ensuring the processes are running at optimum levels for quality and output. They are experts in mold tooling, die tooling, machining, and assembly techniques, possessing extensive knowledge of the associated manufacturing processes which may include the optimization and standardization of stamping / molding / assembly or other processes within the manufacturing environment. Manufacturing Engineering Teams enable the TE business unit plants to reach TE Operating Advantage (TEOA) requirements, roll out Centers of Excellence (COE), Best Demonstrated Practices (BDP s) and advise plants on tool and machine duplications / corrections / improvements. They design and develop manufacturing process and automation platforms and apply them for the realization of new product developments as well as optimization of existing products already in production. The Teams also support Product Development in the selection and optimization of tools for piece part production and the selection of the most suitable manufacturing concepts relative to planned manufacturing quantities, quality requirements and manufacturing location. They act as interface between engineering and production to ensure manufacturability of new designs and smooth production ramp up as well as support the research & development teams to produce sample manufacturing equipment, product samples and prototypes. Responsibility: Analyze new technology and manufacturing processes. Plan and assess the feasibility of new and running projects. Hands on experience in new product development, costing , establish components with optimized CT. Responsible for programming turn, mill, mill-turn, multi-axis machine and process. Product estimation & product costing for machined components, subcon activities, standard parts & assembly process, make vs buy analysis as per scope of supply. Implementing digital factory, cloud-based systems, AI Vision, AR/VR, IOT, Industry 4.0, Machine connectivity, Traceability Systems through wi-fi as well as wired network. Vendor management, Installation, and commissioning of new Equipment s and co-ordinate with Vendor/CFT for complete process validation. Establish tooling, gauge & review fixture designs, CPC calculation and proving out FAI parts and coordinating with shopfloor for mass production. Develop new process , tooling s and create all process documents like PFC, PFMEA, Control plan and SOP by understanding the depth of product requirements Prepare CT & Investment for new product and always work on to reduce cost by optimization/automating process to reduce cost. Responsible for ordering spares and vendor management, down time reduction Capacity & Layout planning/execution for new product line. Support manufacturing for Continuous Improvement, quality issues on the floor, new launches, engineering changes and Lessons Learnt. Develop and implement systems that optimize all phases of production process. Conduct Root-Cause Analysis. Review designs for manufacturing feasibility, suggest changes to the design to ensure product cost effectiveness Establish Tool management System (TMS), Calibration management, Document management Systems like Vicidocs, IQ-RM, Etc. Implement Process monitoring and Control (SPC & SQC), quality traceability Systems using IOT technology. Hands on experience on mechanical 3D design software s like CAD/CAM , NX CAM, NX CAD, Solid CAM, Vericut, SAP MM, TCL & C Language (Basic Desired Candidate Profile EDUCATIONAL/CRITICAL EXPERIENCE B.E./B. Tech in Electrical, Electronics, Mechanical, Mechatronics, or similar technical field. MBA in Marketing would be an added advantage KEY COMPETENCIES Strong analytical thinking and eagerness to learn about product development and market dynamics. Effective communication and collaboration skills across technical and non-technical teams. Basic knowledge or exposure to CAD tools, technical drawings, or electrical/mechanical components are a plus. Familiarity with Excel, PowerPoint, and willingness to learn tools like Power BI or Salesforce. Passionate about making a real-world impact through innovative product design and business alignment. Knowledge of basic electrical and electronics circuits, statistical analysis tools and data analysis Competencies EOE, Including Disability/Vets Location
Posted 2 months ago
3.0 years
0 Lacs
Pune, Maharashtra, India
On-site
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities Digital design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools PPA characterization and optimization of these performance-oriented and power-oriented best-in-class IP cores for advanced process nodes, such as 7nm/5nm/3nm/2nm Development, automation and maintenance of EDA flows and scripts for physical implementation Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs Participate in benchmarking PPAs for customer engagements Required Skills – Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes 3+ years of relevant experience in ASIC design environment Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification Experience with Cadence digital design tools will be an added advantage Hands on scripting languages like Python, Perl, TCL, Unix shell etc Strong understanding of digital logic design, processor design, and computer architecture is desirable Should have excellent communication, analytical and problem solving skills Should be self-motivated and good team player We’re doing work that matters. Help us solve what others can’t. Show more Show less
Posted 2 months ago
8.0 years
0 Lacs
Pune, Maharashtra, India
On-site
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system‐level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Lead DV efforts for blocks, subsystems, and top-level verification. Develop and maintain UVM-based verification environments. Define and review test plans with architecture and design teams. Verify designs using directed and constrained random techniques. Maintain regression, debug failures, and analyze coverage. Drive verification to meet coverage targets. Contribute to next-gen data processing and hardware accelerator verification. Focus on networking domain verification for future solutions. Ensure design closure using innovative and automated techniques. What We're Looking For Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Strong experience with Verilog, SystemVerilog, and UVM. Expertise in unit and subsystem verification, modern verification concepts. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred). Strong debugging skills and verification flow optimization. Collaborate with design teams on specs, test plans, and verification strategies. Develop and maintain UVM-based testbenches for ASIC SoCs. Execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less
Posted 2 months ago
0 years
0 Lacs
Bengaluru, Karnataka, India
On-site
Description As a Electrical Validation Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will create, define and develop electrical validation environment and test suites. You will also be responsible for the development of methodologies, execution of validation plans, debug of failures and follow up to closure. Key job responsibilities Role You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Software Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will: Perform electrical compliance test specifications / compliance test suite for various interfaces and conduct lab measurements Work on high-speed serial I/O interfaces like (LP)DDR4/5, USB, CSI/DSI, HDMI, PCIe interfaces etc. Perform documentation and communicate data across large number of tests and measurement results Drive initiatives to improve process, procedures, and quality of High Speed Characterization at SOC & Product level. Work on schematic and PCB physical design tools to interpret the design and locate physical probe points. Basic Qualifications Bachelor’s degree or higher in EE, ECE, or CS High speed serial interface analog building blocks, protocol, specifications and test methods Writing Python/TCL/PERL code to automate test procedures Good software architecture principles and development practices PCB layout best practices Preferred Qualifications MS/ME in Computer Science, Electrical Engineering, or related field Proficiency in handling High Bandwidth oscilloscopes, BERT, logic analyzers and understanding of probing techniques Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc. Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus. Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable. Familiarity with Transmitter and Receiver design blocks. Understanding of equalization techniques (CTLE/DFE). Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Company - ADCI - BLR 14 SEZ Job ID: A2866703 Show more Show less
Posted 2 months ago
3.0 - 5.0 years
4 - 7 Lacs
Hyderabad
Work from Office
Role & responsibilities Expertise with FPGA debug and HW testing - Using ChipScope Expertise with Board debug using Oscilloscope, Power supplies Ability to read and understand PCB Schematics, layout files RTL Coding in Verilog, System Verilog or VHDL Strong understanding of FPGA flow, Logic design, Digital design etc. Knowledge in Xilinx FPGA architecture Good Knowledge in Tcl, Python scripting Preferred candidate profile Ability to communicate technical information in an organized and understandable fashion. • Customer oriented approach with a demonstrated concern and desire to work with and assist customers. • Good organizational skills with the ability to multitask, prioritize, and track many activities. • Outstanding oral and written communication skills.
Posted 2 months ago
4.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience required 8+ Years. Emulation experience on any available platforms (Palladium, Veloce or Zebu) including bring-up, VIP interfacing, build flow, debug, performance/throughput measurement Good understanding of the SOC designs and verification aspects Experience with Verilog, System Verilog, UVM, SVA Knowledge of communication/interface protocols would be a plus: PCIe, USB3/4, LPDDR5/4 , QUP, eMMC, SD, UFS Knowledge of the processor RISCV, ARM Knowledge of GLS and GLE flows would be a plus Proficient in writing scripts using any languages (Perl, TCL, bash, Python) Experience with waveform debug tools like Verdi Strong communication skills and ability to work as a team with multiple stakeholders Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073184 Show more Show less
Posted 2 months ago
12.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 12+ years of Hardware Engineering or related work experience. Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ year of Hardware Engineering or related work experience. PhD in Computer Science, Electrical/Electronics Engineering, Engineering, with 8+ years of related work experience STA/Timing CAD Methodology Lead As an STA CAD methodology lead, the role would expect the candidate to lead deployment of new features and or methodologies related to STA and ECO domain Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few) There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Key Requirements Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. 10 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Strong understanding of advanced STA concepts and challenges in advanced nodes Proficiency scripting languages (TCL, Perl, Python). Strong background in PNR and Extraction domain. Experience of constraints development tool (like spyglass) will be added advantage. Leadership qualities to lead (technically) and manage the STA CAD team Qualification BE/BTech + 12 years of experience, or ME/MTech + 10 years of experience Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Preferred Qualifications Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 12+ years of Hardware Engineering or related work experience. 3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 3+ years of experience utilizing schematic capture and circuit stimulation software. 3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties And Responsibilities Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers. Level Of Responsibility Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3065939 Show more Show less
Posted 2 months ago
3.0 years
0 Lacs
Noida, Uttar Pradesh, India
On-site
Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073060 Show more Show less
Posted 2 months ago
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