1631 Tcl Jobs - Page 42

AV-273335 Ahmedabad,Gujarāt,India Full-time Permanent 48 eCommerce Solutions Blue Dart Express Limited Job Title Executive - TCL Operations Function Operations Reporting to Manager - TCL Operations 1. Purpose Support all activities relating to operations of Temperature Control Logistics (TCL) shipments across the organization 2. Key Responsibilities Responsibilities Operational Support in Formulation and driving the strategy for Temperature Control Logistics (TCL) operations across the organization Monitor and control all TCL packaging and storing related costs Support in designing and developing the policies, procedures and Standard Operating Procedures (SOPs) for TCL operations Support the planning, monitoring and controlling of all aspects of TCL shipments, to deliver customized solutions and improvements in service and cost performance Responsible for management of day to day operations of TCL shipments, across all locations as per SOPs Monitor the customer requirements for TCL to ensure, they are completed and delivered on time and within the correct temperature range Drive appropriate handling of TCL shipments as per customer specifications (temperature) through measures including use of appropriate packaging, monitoring of package temperatures, sending pre-alerts to locations for TCL shipments, etc. Oversee coordination with customers, regional sales teams, regional operations teams and any other relevant department to ensure delivery as per customer requirements Responsible for maintenance of all packaging inventory as per SOPs Drive appropriate handling and maintenance of freezers/ cold rooms and all TCL inventory and equipments including gel packs, temperature loggers, etc. Play an active role in the identification and empanelment of vendors for supply of dry ice as per organization requirements Play an active role in the development and sourcing of packaging solutions for TCL shipments and liaison with vendors (including international vendors) for the same Support in conduction of regular trainings of TCL operations staff on aspects related to preservation, handling, storing, and maintenance of TCL shipments Monitor the overall service quality of TCL operations and take necessary corrective action (as required) in coordination with the relevant departments 3. Key Result Areas and Key Performance Indicators S. No Key Result Areas Key Performance Indicators 1. Optimization of operating costs % reduction in overall Operating Costs (i.e. OCPK, OCPM) for TCL shipments 2. Reach Enhancement Number of new Pin Codes added for TCL Shipments 3. Drive overall operational performance for TCL shipments Overall service quality for TCL Shipments in terms of Net Service Levels (NSLs) Achievement of target NPS Scores for TCL Shipments % shipments rejected by customer on account of incorrect temperature during transit (data obtained from time loggers) 4. Ensure setup of effective operations processes and policies for TCL product Design and implement processes and SOPs for TCL as per plan Support in new product development for TCL( from an operational point of view) 5. Drive Employee Capability Building for Operations Design of operations training programmes for TCL operations teams as per timelines Conduct/ delivery of TCL operations training programs as per plan % coverage of TCL operations staff (as per plan) in terms of TCL training programmes

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply! About The Role We are looking for an experienced Principal Physical Design Engineer (CAD) to join our small but growing Processor Design group, advancing the art of high performance implementation and physical design. deal candidates will develop and maintain physical design flows for high performance designs. What You’ll Achieve Develop and support innovative physical design methodology and custom CAD Work closely with implementation and physical design (PD) team Debugging flow issues Running multiple test designs through flow on latest technologies to determine impact on technology changes to area, power and timing Automating new flow practices for general use in the design community About You M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in physical design CAD flow including synthesis, place & route, and floor planning Preferred - power distribution, static timing analysis and physical design verification Experience in hierarchical P&R and flow development. Experience with all aspects of PD including floorplanning, power-distribution, pad ring construction, placement, CTS, and routing. Understand hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.) Strong TCL/Perl/Makefile scripting knowledge. Experience in developing complex algorithms, managing, and regressing P&R flows. Familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies. Good communication and problem-solving skills What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

JOB description 4-14years Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience. Show more Show less

Job Details: : In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII. You will be part of ACE Group, in the P-Core design team driving Intels latest CPUs in the latest process technology. Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design.Static timing analysis. Power OptimizationDesign Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute Scale and Performance engineer shall be responsible for validating feature scale and performance, run manual or automation S&P tests against all supported features developed across Ciena's Routing and Switching platform portfolio. Work involves scale and performance validation along robustness test and automate test plans to verify product capabilities. Execution of feature scale test-plans, test bed design, test topologies, Test Automation & test Executions. Set up complex test beds based on Project requirements. Assist development engineers in product defect diagnosis/debugging and verification of fixes. Day-to-day activities include planning, designing, automating, and validating tests around scale, performance, longevity and robustness tests across all supported features or feature combinations (Uni-D and Multi-D) to validate system behavior at limit and endurance. Develop test-plans, plan and design test-topologies and test methodologies with optimal resource usage. Prepare/Automate robust, quality, S&P scripts with robustness and longevity also in perspective with optimal CPU and memory measurement reading mechanisms, and feature/systemic performance measurement mechanisms. Use JIRA to file defects following proper template, and all logs/debug command output/traffic flow footprint, etc. relevant to the problem description. Assist development engineers in product defect diagnosis/debugging/reproduction and verification of fixes. Execution of test cases and reporting test results with artifacts using Test Rail Work closely with engineers across teams/geographies to ensure quality for the features. Position requires troubleshooting and problem-solving skills Understand Software Development Life Cycle. Conducts Knowledge Sharing Sessions (Desirable): Basic to moderate topics, including specific product feature or functional areas related the assigned features. Able to manage feature and schedule churns with minimal guidance. Contribute to team deliverable through involvement in agile scrum development sprints. The Must Haves 5-8 years of experience in telecommunication and testing. Experience with Python/Tcl/Expect is a must. Fluency and experience in data communication systems, networking, Ethernet switches and Routers. Hands-on experience with L2/L3 topologies. Strong testing experience in some of the Layer-2 protocols like Ethernet Switching, VLANs, G.8032, CFM,Y.1731,BFD,VPLS,VPWS,QoS and L3 protocols like BGP, IS-IS, OSPF Working experience in areas like EVPN, L2VPN,L3VPN and in transports like MPLS,SR,LDP,RSVP Experience with traffic generators such as Ixia, Spirent. The Good To Haves Good knowledge of network design and deployment scenarios in Carrier/Metro Ethernet Space is plus. Netconf/GNMI/Telemetry exposure is an added advantage. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less

As a Senior Officer in the IDT_BA_GCC department, you will be responsible for managing and overseeing the indirect taxation processes of the organization. You will be expected to have a strong understanding of regulatory acts and laws, and be proficient in using accounting software. Your role will also require you to have a basic understanding of legal matters related to indirect taxation.

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: Scale and Performance engineer shall be responsible for validating feature scale and performance, run manual or automation S&P tests against all supported features developed across Ciena's Routing and Switching platform portfolio. Work involves scale and performance validation along robustness test and automate test plans to verify product capabilities. Execution of feature scale test-plans, test bed design, test topologies, Test Automation & test Executions. Set up complex test beds based on Project requirements. Assist development engineers in product defect diagnosis/debugging and verification of fixes. Day-to-day activities include planning, designing, automating, and validating tests around scale, performance, longevity and robustness tests across all supported features or feature combinations (Uni-D and Multi-D) to validate system behavior at limit and endurance. Develop test-plans, plan and design test-topologies and test methodologies with optimal resource usage. Prepare/Automate robust, quality, S&P scripts with robustness and longevity also in perspective with optimal CPU and memory measurement reading mechanisms, and feature/systemic performance measurement mechanisms. Use JIRA to file defects following proper template, and all logs/debug command output/traffic flow footprint, etc. relevant to the problem description. Assist development engineers in product defect diagnosis/debugging/reproduction and verification of fixes. Execution of test cases and reporting test results with artifacts using Test Rail Work closely with engineers across teams/geographies to ensure quality for the features. Position requires troubleshooting and problem-solving skills Understand Software Development Life Cycle. Conducts Knowledge Sharing Sessions (Desirable): Basic to moderate topics, including specific product feature or functional areas related the assigned features. Able to manage feature and schedule churns with minimal guidance. Contribute to team deliverable through involvement in agile scrum development sprints. The Must Haves: 5-8 years of experience in telecommunication and testing. Experience with Python/Tcl/Expect is a must. Fluency and experience in data communication systems, networking, Ethernet switches and Routers. Hands-on experience with L2/L3 topologies. Strong testing experience in some of the Layer-2 protocols like Ethernet Switching, VLANs, G.8032, CFM,Y.1731,BFD,VPLS,VPWS,QoS and L3 protocols like BGP, IS-IS, OSPF Working experience in areas like EVPN, L2VPN,L3VPN and in transports like MPLS,SR,LDP,RSVP Experience with traffic generators such as Ixia, Spirent. The Good To Haves: Good knowledge of network design and deployment scenarios in Carrier/Metro Ethernet Space is plus. Netconf/GNMI/Telemetry exposure is an added advantage. #LI-Hk1 Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

*Key Responsibilities:* - *Designing and Developing Hardware Components*: Create detailed schematics, PCB layouts, and technical drawings using CAD software. - *Testing and Validation*: Conduct thorough testing and validation of hardware components to ensure functionality and reliability. - *Collaboration*: Work closely with cross-functional teams, including software engineers, product managers, and manufacturing teams. - *Troubleshooting*: Identify and resolve hardware issues during design and testing phases. - *Project Management*: Manage hardware projects, including project planning, resource allocation, and risk assessment. *Design and Development:* - Develop embedded digital systems incorporating microprocessors and FPGAs. - Design simulations using pSPICE, LTSpice, and other relevant software. - Create technical specifications and diagrams to guide manufacturing and assembly processes. - Optimize hardware designs for cost, performance, and reliability ¹ ² ³. *Requirements and Qualifications:* - Bachelor's degree in Electrical Engineering, Computer Science, or a related field. - Proven experience as a Hardware Design Engineer or in a similar role. - Experience with computer-aided design (CAD) software. - Strong understanding of electronic systems and component materials. - Excellent communication and teamwork abilities ⁴ ⁵. *Nice to Have:* - Experience with IoT design, SMPS, and high-level programming languages like C/C++ and scripting languages like Perl/TCL/Python. - Knowledge of signal processing and data acquisition. - Familiarity with industry standards and regulations ¹ ³. Job Type: Full-time Pay: ₹204,947.50 - ₹979,980.99 per year Schedule: Day shift Application Question(s): Immediat joiner? Work Location: In person

Who We Are At Kyndryl, we design, build, manage and modernize the mission-critical technology systems that the world depends on every day. So why work at Kyndryl? We are always moving forward – always pushing ourselves to go further in our efforts to build a more equitable, inclusive world for our employees, our customers and our communities. The Role Are you passionate about solving complex problems? Do you thrive in a fast-paced environment? Then there’s a good chance you will love being a part of our Software Engineering – Development team at Kyndryl, where you will be able to see the immediate value of your work. As a Software Engineering - Developer at Kyndryl, you will be at the forefront of designing, developing, and implementing cutting-edge software solutions. Your work will play a critical role in our business offering, your code will deliver value to our customers faster than ever before, and your attention to detail and commitment to quality will be critical in ensuring the success of our products. Using design documentation and functional programming specifications, you will be responsible for implementing identified components. You will ensure that implemented components are appropriately documented, unit-tested, and ready for integration into the final product. You will have the opportunity to architect the solution, test the code, and deploy and build a CI/CD pipeline for it. As a valued member of our team, you will provide work estimates for assigned development work, and guide features, functional objectives, or technologies being built for interested parties. Your contributions will have a significant impact on our products' success, and you will be part of a team that is passionate about innovation, creativity, and excellence. Above all else, you will have the freedom to drive innovation and take ownership of your work while honing your problem-solving, collaboration, and automation skills. Together, we can make a difference in the world of cloud-based managed services. Your Future at Kyndryl The career path ahead is full of exciting opportunities to grow and advance within the job family. With dedication and hard work, you can climb the ladder to higher bands, achieving coveted positions such as Principal Engineer or Vice President of Software. These roles not only offer the chance to inspire and innovate, but also bring with them a sense of pride and accomplishment for having reached the pinnacle of your career in the software industry. Who You Are You’re good at what you do and possess the required experience to prove it. However, equally as important – you have a growth mindset; keen to drive your own personal and professional development. You are customer-focused – someone who prioritizes customer success in their work. And finally, you’re open and borderless – naturally inclusive in how you work with others. Required Technical and Professional Experience Minimum exp 4 to 6 years of experience. Education qualification- Any Graduate. BCP-DR Application Architecture Your understanding customer IT-DR for On-Prime/Off-Prime/Hybrid Infrastructure for the application. Your understanding DR-DRILL to map them into Kyndryl Resiliency Orchestration solution (Sanovi DRM solution) Content Maintenance Perform updates, revisions Materials subject to maintenance include: LLD, HDL, Solution Design/Approach document, Technical Reports, PPTS etc. Experience in Linux and any database (Oracle, MySQL). Strong understanding of the Data Protection (Back-up & Recovery, BCP DR, Storage Replication, Database Native Replications, Data Archival & Retention) for application workloads such as MS SQL, Exchange, Oracle, VMware, Hyper-V, azure, AWS etc. Extremely good hands-on experience with Standalone and Clustered UNIX (AIX/Solaris/HPUX/RHEL/etc.) and windows platform. TCL/Shell/Batch/PowerShell/Expect Scripts or similar scripting languages is must. Should be able to write scripts to integrate with different technologies using CLI's /API's. Understand and strong knowledge of any Storage Replication technology with various DR Scenarios. Should be able to design/architect and build LLD, HLD, Implementation. Application testing experience may be added advantage Overall IT Infrastructure understanding is an added advantage Cyber (IT) Security related experience is an added advantage. Keep management and stakeholders informed about the status of disaster recovery preparedness, including risks, progress, and improvements. Should know about Zerto and Arcon tool exp. Preferred Technical and Professional Experience Hands on knowledge of Disaster recovery tool. Hands on experience on Linux administration and excellent scripting knowledge. 10 years of experience in Disaster recovery practice with experience in Banking, Manufacturing, Insurance and BFSI clients. Being You Diversity is a whole lot more than what we look like or where we come from, it’s how we think and who we are. We welcome people of all cultures, backgrounds, and experiences. But we’re not doing it single-handily: Our Kyndryl Inclusion Networks are only one of many ways we create a workplace where all Kyndryls can find and provide support and advice. This dedication to welcoming everyone into our company means that Kyndryl gives you – and everyone next to you – the ability to bring your whole self to work, individually and collectively, and support the activation of our equitable culture. That’s the Kyndryl Way. What You Can Expect With state-of-the-art resources and Fortune 100 clients, every day is an opportunity to innovate, build new capabilities, new relationships, new processes, and new value. Kyndryl cares about your well-being and prides itself on offering benefits that give you choice, reflect the diversity of our employees and support you and your family through the moments that matter – wherever you are in your life journey. Our employee learning programs give you access to the best learning in the industry to receive certifications, including Microsoft, Google, Amazon, Skillsoft, and many more. Through our company-wide volunteering and giving platform, you can donate, start fundraisers, volunteer, and search over 2 million non-profit organizations. At Kyndryl, we invest heavily in you, we want you to succeed so that together, we will all succeed. Get Referred! If you know someone that works at Kyndryl, when asked ‘How Did You Hear About Us’ during the application process, select ‘Employee Referral’ and enter your contact's Kyndryl email address.

Role & responsibilities Develop and customize Teamcenter PLM solutions based on business requirements. Create and maintain Teamcenter modules, workflows, and processes. Implement customizations using BMIDE (Business Modeler IDE) and other tools to extend Teamcenter functionality. Work on Teamcenter integrations with other enterprise systems such as ERP, CAD, and MES. Develop and implement custom API and web services for seamless communication between Teamcenter and external systems. Utilize programming languages such as Java, C++, and ITK (Integration Toolkit) for customization and extension of Teamcenter. Provide day-to-day technical support to users and troubleshoot issues related to Teamcenter. Resolve system errors, performance issues, and software bugs in a timely manner. Perform system upgrades and patches as needed. Develop test plans, test cases, and perform system testing to ensure Teamcenter solutions meet business requirements and quality standards. Document code, processes, and customizations to ensure maintainability and consistency. Collaborate with business analysts and project managers to understand requirements and translate them into technical solutions. Work closely with cross-functional teams such as IT, PLM specialists, and business users to ensure proper implementation and adoption of Teamcenter solutions. Assist in training and mentoring junior developers and team members. Preferred candidate profile Must have hands-on experience working with Teamcenter 10 Java / J2EE and C / C++ programming languages Advanced Eclipse framework IDE Functional Siemens Teamcenter PLM BMIDE (Business Model Integrated Dev. Environment) Functional Siemens Teamcenter PLM ITK (Integrated Toolkit) Advanced Siemens Teamcenter PLM SOA (Service Oriented Architecture) Functional Siemens Teamcenter PLM Workflow / Custom Handler development Advanced NX UFUNC programming Experience with scripting languages like Shell/Perl/python/TCL. Work Location- All India

Requirement: Java Trainer ExcelR is seeking an experienced and passionate Freelance Trainer for our comprehensive Full Stack Web Development Program. You will train aspiring developers through a 50-day structured curriculum Offline at College Campus focused on real-world application development and end-to-end deployment.🧑‍💻 What You’ll Teach (Curriculum Overview) ✅ Frontend Development HTML5: Text, Media, Forms, Tables, Semantic Tags, Meta Tags CSS3: Box Model, Flexbox, CSS Grid, Responsive Design, Pseudo-classes, Transitions JavaScript ReactJS: JSX, Components, State, Props, useEffect, useRef, useMemo, Forms, Routing Bootstrap Mini Projects & CRUD App Frontend Deployment & Interview Prep ✅ Backend Development Java Node.js & Express.js REST API design and integration ✅ Database Skills (10 Days) MySQL SQL Queries, Joins, Aggregations DDL, DML, TCL Commands Analytical/Window Functions 📌 Requirements Proven experience as a Full Stack Developer or Trainer Hands-on expertise with HTML, CSS, JS, React, Django/FastAPI/Node.js Strong SQL skills (MySQL) Prior teaching/training/mentoring experience preferred Excellent communication and presentation skills Ability to explain complex topics to beginners effectively Comfortable using Zoom, Google Meet, or Microsoft Teams 🎯 Preferred Qualifications B.Tech/B.E ,M.Tech/M.E in Computer Science Engineering Field. 5+ Years Experience delivering training in bootcamp or corporate environments Familiarity with online learning tools and live coding sessions Show more Show less

Role & responsibilities Technologies with sound knowledge WLAN IEEE802.11 a/b/g/n/ac/ax/be Test experience Ethernet & Wired networking (added advantage) Independent Project handling with analytical ability Testing Experience Functional WLAN tests Protocols/Layers with good theoretical & practical knowledge Sound knowledge on Layer 1, 2, 3, IEEE802.11 a/b/g/n/ac/ax/be Knowledge on WPA2/WPA3, MU-MIMO, OFDMA, Beamforming, Roaming etc Traffic Generators Understating and Usage of Traffic generator tools like Spirent / Ixia / Chariot/ Veriwave. Knowledge on RFC2544, RFC2889, RFC3918 tests etc. Traffic Analyzers Wireshark, Ethereal, airopeak/omnipeak Operating Systems Windows 10/XP/Win7, Linux Automation Scripting Knowledge of Automation Scripts is mandatory Python / Perl / TCL

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Qualifications 8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. Education A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

The candidate will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. REQUIREMENTS: 4-9 years of experience in ASIC Physical Design Have good Hands on entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have hands-on experience in latest sub-micron technologies below 7nm Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Location :: Hyderabad & Bangalore *Adds on advantage atleast one or two projects has worked in AMD projects in his / her carier. Thanks, P Mohankrishna, Mohankrishna.p@Altcognitosystems.com Show more Show less

Requirement: Java Trainer ExcelR is seeking an experienced and passionate Freelance Trainer for our comprehensive Full Stack Web Development Program. You will train aspiring developers through a 50-day structured curriculum Offline at College Campus focused on real-world application development and end-to-end deployment.🧑‍💻 What You’ll Teach (Curriculum Overview) ✅ Frontend Development HTML5: Text, Media, Forms, Tables, Semantic Tags, Meta Tags CSS3: Box Model, Flexbox, CSS Grid, Responsive Design, Pseudo-classes, Transitions JavaScript ReactJS: JSX, Components, State, Props, useEffect, useRef, useMemo, Forms, Routing Bootstrap Mini Projects & CRUD App Frontend Deployment & Interview Prep ✅ Backend Development Java Node.js & Express.js REST API design and integration ✅ Database Skills (10 Days) MySQL SQL Queries, Joins, Aggregations DDL, DML, TCL Commands Analytical/Window Functions 📌 Requirements Proven experience as a Full Stack Developer or Trainer Hands-on expertise with HTML, CSS, JS, React, Django/FastAPI/Node.js Strong SQL skills (MySQL) Prior teaching/training/mentoring experience preferred Excellent communication and presentation skills Ability to explain complex topics to beginners effectively Comfortable using Zoom, Google Meet, or Microsoft Teams 🎯 Preferred Qualifications B.Tech/B.E ,M.Tech/M.E in Computer Science Engineering Field. 5+ Years Experience delivering training in bootcamp or corporate environments Familiarity with online learning tools and live coding sessions Show more Show less

Company Description MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers located in Silicon Valley, USA, and India. Our expertise includes end-to-end silicon design, verification, systems, software, and device engineering, along with AI/ML solutions and test automation. MosChip® has an impressive track record with first-time right silicon of over 200 SoC tape-outs and has shipped millions of connectivity ICs. We provide comprehensive services including Digital IPs, Verification IPs, Mixed Signal IPs development, and Turnkey ASIC services. Role Description This is a full-time on-site role for a Senior Lead Physical Design Engineer located in Hyderabad. The Senior Lead Physical Design Engineer will be responsible for the complete physical design flow including, but not limited to, floorplanning, power planning, place and route, clock tree synthesis, and physical verification. The individual will also collaborate with cross-functional teams to ensure design specifications are met, timing closure is achieved, and design targets are aligned with company standards and customer expectations. Qualifications He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks’ closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs. Show more Show less

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIA's unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain. What You'll Be Doing As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's. Develop and own verification environment using UVM or equivalent. Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards. Own functional coverage driven verification closure and own design verification sign-offs at multiple levels. Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams. Will be part of innovation to strive to improve the quality of DFT methods What We Need To See BSEE with 3+ or MSEE with 2+ years of experience in IP verification or related domains Expertise in System Verilog and verification methodologies like UVM/VMM. Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc). Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures. Strong programming/scripting skills in C++, Perl, Python or Tcl Excellent written and oral communication skills Excitement to work on rare challenges Strong analytical and problem solving skills Ways To Stand Out From The Crowd Strong experience or interest in both DFT and RTL Verification domains Knowledge in Formal verification methodologies and tools for IP and SoC level verification Hands-on experience in post silicon debug on ATE and/or system labs. JR1998780 Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: PD CAD Engineer Location:Hyderabad Work Type: Onsite Job Type: Full time Job Description: KEY RESPONSIBILITIES: Timing analysis and timing closure flow development and support , with focus on Synopsys Prime time, PrimePower, PrimeClosure Tools. Maintain and add enhancements to the AMD PD code flow Work closely with Design teams and EDA vendors to debug and fix issues in the PD flow and tools. Regressions to benchmark new Prime time tool versions PREFERRED EXPERIENCE: Experienced professional in PD, timing signoff and physical design Good understanding of advanced technologies in Prime time like Hyperscale and SMVA Good understanding of Physical Design implementation Good scripting skills in TCL, Perl or Python Work Experience 2-6 years TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Software Engineer (Development and test) Responsible for developing & testing of software Responsible for generating documents, such as design, user-guide, test plan, test spec, test report etc., Skills Must have Candidate should have 5+ yrs experience Experience: Experience in C/C++ programming Experience with Multi-threaded software development in Linux environment Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA Experience with development of software targeted for x86, standalone and RTOS platforms Experience in low level driver development, register interface programming, general algorithms and data structures, bootloaders/Uboot Experience with CI tools, test automation, etc. Strong debugging skills at device and board level using JTAG debuggers Experience in Software programming for FPGAs is an advantage Scripting language experience like Perl, Python or TCL Nice to have Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills EducationB.tech/M.Tech in CSE/IT/ECE/EEE/E&I OtherLanguagesEnglishB2 Upper Intermediate SeniorityRegular