1570 Tcl Jobs - Page 4

Join Vanderlande as Director - Accounting, Control & Compliance | Reports to: Managing Director Group Finance & Accounting Take Charge. Step Into a Leadership Role That Drives Innovation in Logistics! Dare to lead where innovation meets precision. If you're a finance leader who thrives on challenge, complexity, and cross-continental impact - this is your next big move. About the Role: Lead, Influence, Transform Were looking for a trailblazing finance leader to elevate our global accounting, control, and compliance strategy . This isnt a back-office role - its your seat at the table to influence real transformation. What Youll Own: Govern global compliance with J-SOX/SOX, tax laws & corporate controls Drive consistency & excellence in financial reporting across international teams Lead powerhouse teams in India and partner with EMEA, Americas & APAC Challenge the ordinary automate, improve, and elevate finance systems & strategy You Bring: 18+ years of experience in accounting, compliance, and control (MNC preferred) Deep expertise in IFRS , J-SOX/SOX , tax compliance , and ERP systems Exceptional leadership in hybrid and matrix team models A strategic mind with a >

#Urgent_Opening_for Canvendor #Hiring: DV Engineer (10+ Years Experience) | Pune| Immediate Joiners Preferred Location: Pune, India Experience: 10+ Years Notice period: Immediate to 30days Skills Highlighted: Key Requirements: -Bachelor’s degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines, with 10 years of experience. -Understanding of SoC architecture and functionality -Understanding of directed and constrained random verification methodology -Good knowledge in UVM, Verilog, System Verilog, C/C++, Shell -Good software programming skills are important therefore -Good knowledge in Scripting like Perl, TCL or Python is a plus -Good communication skills to interact with teams across the globe and work independently If interested kindly share your updated CV to anushab@canvendor.com

Our Purpose Mastercard powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title And Summary Senior Software Engineer Overview This contractor position is on Mastercard’s performance engineering team working closely with the other Authorization development teams. You will have the chance to use and improve a suite of tools to assess transaction time each release. We are looking for engineers that are passionate about performance and development with a constant focus on improving quality. All About You Have you created many scripts to automate and interface with programs (i.e. shell script, TCL, Perl, Python)? Do you understand throughput, latency, memory, and CPU utilization? Have you spent significant time in Linux environments with some experience administrating? Have you developed software before – preferably in C/C++? Do you know about different inter-process communications (i.e. shared memory, MQ, Kafka)? Do you have experience and prefer working in an Agile environment? Have you worked with big, real-time, and distributed systems? Design, configure, and execute performance tests Work closely with software development teams to identify risks and anticipate problems to ensure that each release does not negatively impact performance Improve the current performance environment with your own code, automation, and onboarding of external tools (i.e. Dynatrace and Splunk) Drive performance issues to resolution Corporate Security Responsibility All Activities Involving Access To Mastercard Assets, Information, And Networks Comes With An Inherent Risk To The Organization And, Therefore, It Is Expected That Every Person Working For, Or On Behalf Of, Mastercard Is Responsible For Information Security And Must: Abide by Mastercard’s security policies and practices; Ensure the confidentiality and integrity of the information being accessed; Report any suspected information security violation or breach, and Complete all periodic mandatory security trainings in accordance with Mastercard’s guidelines.

As a Physical Design Engineer, you will be responsible for top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You should have experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentoring to Physical Design Engineers and interface with front-end ASIC teams to resolve issues related to low power design techniques. Your responsibilities will also include timing closure on DDR2/DDR3/PCIE interfaces, ensuring excellent communication skills, and possessing a strong background in ASIC Physical Design encompassing Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. You should have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools, expertise in scripting languages such as PERL, TCL, strong Physical Verification skill set, and proficiency in Static Timing Analysis in Primetime or Primetime-SI. In addition to technical responsibilities, you should have good written and oral communication skills, the ability to clearly document plans, and the capability to interface with different teams and prioritize work based on project needs. Qualifications: - Experience: 5 to 8 Years Location: - Hyderabad,

The Core Switch Group (CSG) at Broadcom, the industry leader in cutting-edge networking ASICs, is known for developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team has contributed to iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazine's "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If you're a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities: - Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon. - Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. - Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium. - Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. - Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. - Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. - Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans. - Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. - Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring: - Bachelors with 12+ years in emulation or post-silicon validation of networking ASICs. - Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. - Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable. - Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. - Excellent communicator who thrives in a collaborative, fast-paced environment.,

In Dassault Systemes Global Services, we are looking for a strongly motivated Software Engineering Specialist who will contribute to the organization via their technical, functional, and consulting skills. There are many applications available as part of the 3DEXPERIENCE ENOVIA platform, previously called Centrals. Each application represents a set of features that represent one or more processes needed in one or more industries. These apps provide a vast set of features and functions to satisfy customer requirements and help build customer processes. We are seeking a resource with experience in configurations, customizations, upgrades, new development, and integrations primarily related to apps in 3DSpace & 3DDashboard. The ability to understand and analyze requirements, develop functional/technical specifications, and proficiency in customer interfacing/communication is essential. This position is based in our office located in Pune, India. Role Description & Responsibilities: - Understand customer business requirements, scenarios, use cases, and user experience needs. - Translate specification dossiers reported by global solution architects into detailed technical specifications. - Evaluate/estimate (man/days), manage activities to ensure delivery deadlines, and report to global solution architects. - Describe software system design in technical terms, plan appropriate user interfaces, select algorithms, theories, or technologies, and manage dependencies with other components. - Support/contribute to development activities including investigation, design, coding, unit & functional testing. - Execute steps to upgrade the ENOVIAV6/3DEXPERIENCE platform to the targeted release in case of upgrades. Identify the Schema/Web files to be upgraded, and Data migration scripts to be executed. Qualifications: - Degree in Engineering or Computer Science. - Experience required: 3-7 years. - Experience in working on ENOVIA V6 or 3DEXPERIENCE implementation, integration, and upgrade projects. - Experience in technical/functional 3DEXPERIENCE project definition/execution. - Experience in technical consulting, solution design, project envisioning, planning, development, and deployment. - Strong knowledge of 3DS products and technologies. - Hands-on development experience in Core Java, J2EE, JPOs, rest-based web services. - Good knowledge of MQL, TCL. - Experience in identifying, planning, and executing system upgrades including schema & files customizations to the targeted version. - Good to have knowledge/experience in 3DDashboard widget development, web technologies, ability to build new interfaces using JavaScript, jQuery, HTML, CSS, JS frameworks (Like Angular/React/Vue JS), REST web services backend, and building on demand/real-time/messaging queue-based integrations & batch processes. What's In It For You: - Work in a culture of collaboration and innovation. - Be at the forefront of building software products deployed in mission-critical projects worldwide. - Be offered avenues to develop yourself for career progression. - Not a low-level development opportunity, as you would get to work in the real business world and with a wide range of customers & coworkers. - Work on a variety of technologies, products, and solutions. Diversity Statement: As a game-changer in sustainable technology and innovation, Dassault Systmes is striving to build more inclusive and diverse teams across the globe. We believe that our people are our number one asset and we want all employees to feel empowered to bring their whole selves to work every day. It is our goal that our people feel a sense of pride and a passion for belonging. As a company leading change, it's our responsibility to foster opportunities for all people to participate in a harmonized Workforce of the Future.,

Job Description: Experience: 4+ years of Experience Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks o Good to have experience in TSMC/Intel lower technology node(16/14nm or below) o Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build o Basic Timing understanding to independently analyze timing paths o Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage o Basic equivalency check understanding. Good to have Conformal LEC experience. o Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks

Gurugram, Haryana, India Department Sales Job posted on Jul 29, 2025 Employment type Employee We are looking for a detail-oriented and proactive Sales Analyst to join our growing APAC team. This role plays a critical part in supporting the APAC API Team and operations functions by monitoring credit compliance, analyzing booking and revenue trends, resolving key partner issues, and assisting with administrative processes. The ideal candidate should have strong analytical skills, excellent attention to detail, and the ability to coordinate across multiple teams and stakeholders. Key Responsibilities: Credit & Account Monitoring Monitor daily remaining credit for each client and track temporary credit limit (TCL) expiration to ensure compliance and uninterrupted service. Performance & Trend Analysis Conduct daily Net Revenue Margin (NRM) analysis across all clients and provide data-driven suggestions for optimization. Evaluate daily and weekly client booking trends to detect patterns, investigate client drop-offs, and report findings. Track search and error trends, highlighting anomalies for prompt investigation and resolution. Data Coordination & Administrative Support Support mapping file management and data coordination in collaboration with the Customer Success Team. Perform administrative tasks including: Client agency account creation Coordinating with the KYC and Finance Support teams to facilitate credit setup and live credential release Operational Issue Resolution Assist in resolving operations-related disputes, particularly with external partners such as big OTAs, in coordination with internal stakeholders. Refund Support Act as support for refund processing – reviewing cases and ensuring timely updates on refund status. Qualifications & Requirements: Bachelor’s degree in Business, Finance, Economics, or a related field 2–4 years of experience in sales operations, data analysis, or financial coordination Proficient in Microsoft Excel and data analytics tools (e.g., Power BI, Tableau is a plus) Strong attention to detail with an analytical and investigative mindset Ability to multitask, prioritize, and manage time effectively Good communication and coordination skills across internal and external teams

Location Karnataka Bengaluru Experience Range 10 - 15 Years Qualification BE (EEE) Job Description FPGA design Engineer Key skills: Design and implement FPGAs used in distributed antenna and OpenRAN wireless systems Perform architecture trade-off analysis based on design requirements Competency in RTL design (VHDL preferred) Knowledge in digital signal processing (e.g. FFT, IFFT, Filter designs) Familiar with multi gigabit packet communication protocols (Ethernet, JESD204, etc.) and corresponding hardware cores in FPGA Experience with AMD (Xilinx) and/or Altera FPGA platforms Experience with design implementation through timing closure Proficiency in simulation tools (e.g., ModelSim, Vivado Simulator) Good-to-Have: Experience with version control tools (e.g., Git, SVN) Familiarity with scripting languages (TCL, Python, etc.). Experience with Matlab/Simulink. PCB bring-up with FPGA builds

Are you interested in working with a world-class CPU design team at Qualcomm India Private Limited Do you have a passion for applying formal methods to verify application processors and contributing to the development of next-generation formal methodologies Qualcomm's CPU team is at the forefront of developing processors that will power the future. Join us on this exciting adventure and maximize your formal verification skills on complex designs. As a member of the CPU design team, you will collaborate closely with the design team to grasp design intent and establish verification plans with a focus on end-to-end formalization from architecture to micro-architecture refinement. Your responsibilities will include defining formal verification architecture, creating test plans, and constructing formal sign-off environments for Qualcomm CPU components. You will deploy model-checking technology across hardware designs, encompassing property verification, mathematical proofs, architectural modeling, and validation in cutting-edge application areas. To excel in this role, you should hold a BA/BS degree in CS/EE with over 8 years of practical experience in applying formal methods in hardware or software. A solid background in model checking or theorem proving for complex systems is essential. Proficiency in writing assertions, developing modeling code in Hardware Description Languages, or ensuring correctness of architectural specifications using formal methods is required. Familiarity with model checkers like Jaspergold and VC-Formal, or theorem-proving tools such as ACL2 and HOL, is advantageous. The ideal candidate would possess an MS/PhD degree in CS/EE with at least 4 years of practical experience and a strong foundation in formal methods applied to hardware specifications or implementations. Domain knowledge in areas such as microprocessor architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, and security architectures is beneficial. Additionally, strong software engineering skills, automation abilities, and proficiency in programming languages like C++, Python, or TCL are preferred. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 3+ years of Hardware Engineering experience OR - PhD in Computer Science, Electrical/Electronics Engineering, or related field with 2+ years of Hardware Engineering experience Qualcomm is an equal opportunity employer that provides accommodations for individuals with disabilities during the application and hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Qualcomm expects employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. For further information about this role, please reach out to Qualcomm Careers.,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

As an Infrastructure Consultant for the 3DExperience Platform, you will be responsible for ensuring the secure deployment of 3DEXPERIENCE projects by operating and maintaining Solutions Infrastructure in the customer's information system environments. Your role will involve timely resolution of deployment issues, re-use of capitalized assets, ensuring quality and on-time delivery of installations and documentation for 3DExp/platform/Installation/Administration. Your primary focus will be on deploying new solutions on time, even under pressure, to deliver the best services to demanding customers. You should be a fast learner, capable of quickly ramping up on the installation and configuration of the latest version of DS Software. Additionally, you should possess excellent knowledge of system administration and a strong interest in network administration, including load balancing. Basic to intermediate level knowledge of CATIA client is desired, but not a main criteria. Functional knowledge related to Enovia/Matrix One/3DExperience is considered an added advantage. You should hold a degree in software engineering or mechanical engineering with experience in PLM infrastructure implementation. The position is based in Pune/Bangalore and requires 4 to 10 years of experience in the field. Dassault Systmes, as a pioneer in sustainable technology and innovation, is committed to fostering inclusive and diverse teams globally. The company values its employees as the most valuable asset and encourages them to bring their authentic selves to work every day. By promoting a sense of pride and belonging among its employees, the company aims to create a harmonized Workforce of the Future that offers opportunities for all individuals to participate.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and develop innovative solutions. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. You should have 2-6 years of experience in Synthesis, Constraints, and interface timing Challenges, along with a strong domain knowledge in RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog, micro-architecture & designing cores and ASICs, and familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc., will be highly beneficial. Exposure in scripting languages such as Pearl/Python/TCL and strong debugging capabilities are also required for this role. As a Qualcomm Hardware Engineer, you will collaborate closely with cross-functional teams to research, design, and implement performance, constraints, and power management strategies for the product roadmap. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are a proactive team player with the ability to independently debug and solve issues, and meet the qualifications mentioned above, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

You are invited to apply for the position of "ASIC RTL Engineer" at Semi Leaf consulting Service located in Bangalore. With 3-8 years of experience, if you are available to join within 30 days and prefer working in a WFO mode, this opportunity might be just for you. As an ASIC RTL Engineer at Semi Leaf, your responsibilities will include working on ASIC RTL design, RTL Logic Synthesis, LEC, Conformal, ECO, FC Check, and having proficiency in either TCL or Python. You must have Synthesis or Implementation experience, familiarity with the Linux environment, excellent communication skills, and experience with at least one serial protocol like UART, I2C, SPI. Skills with SOC Architecture, experience in CDC and Lint, and working on Cortex-M4 core/Sub-system verification/execution environment bring-up are desirable. Additionally, you should be able to develop verification infrastructure for Cortex-M4 Core/Sub-system bring-up, have knowledge of Coresight/Functional Debug architecture, and expertise in UVM/SV knowledge to develop scoreboard/checkers. If you are interested in this opportunity and possess the required experience, kindly share your updated resume with vagdevi@semi-leaf.com. Referrals are also highly appreciated. Join us at Semi Leaf consulting Service and be part of a team of experts dedicated to finding candidates with specialized skills in Semiconductor/VLSI/EDA & Embedded domains.,

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you, What Youll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes, Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts, Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff, Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges, Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities, Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects, Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization, The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation, Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction, Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes, Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows, Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization, Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement, What Youll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles, Proficiency in TCL, Python, and Make for scripting and automation, Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis, Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax, Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route), Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim, Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation, Effective communicator, able to collaborate across disciplines and share complex ideas clearly, Self-motivated and adaptable, eager to learn new technologies and methods, Detail-oriented with a commitment to delivering high-quality results under tight deadlines, Team player who values diversity, equity, and inclusion in the workplace, The Team Youll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

Roles & Responsibilities : 8-10 Years of relevant Experience in PLM-3DExperience Platform in Customizations, Migrations, Configuration, and Installation Expertise in using ENOVIA toolkit Business, Navigator, Matrix Navigator, MQL, TCL, System, Spinner, UI3 components, JPOs, Triggers, Policy/Workflows, P&O and Enovia APIs. Programming Experience in Java, JSP, HTML, JavaScript and JSON Implementations. Good exposure and working experience in analyzing Functional Specification, High Level Design Documents and Technical Design Documents Experience in working with Agile and Waterfall methodologies Experience in migrating data to ENOVIA using – Java, TCL approaches. Developed several TCL programming Scripts for extracting and updating the existing Production Data Analyzing the functional requirements and translating functional requirements into High Level Designs, Technical requirements and customizing the application Build and developing the logic & writing the code as per the design document. Implementing Business Logic, developing the use cases. Debugging the issue raised by the user is valid /invalid and provides the optimum solution. Validating the impacted functionalities to make sure no regressions occur. Analyzing the requirement and making a draft of the design. Debugging, deploy & Responsible for fixing the bugs if occurred either at schema level or code level. Updating the status of the development to the manager in the weekly meetings. Participate in Design Review Calls with technical architects, get the Design Document reviewed to ensure no impact on other functionalities and get sign off by Technical Architects. Note: Notice Period should be Immediate to 15 days maximum Interested Candidates please share your resume to below contact Regards, Geethika 9182749034 Geethika@megconsulting.in

Your team The PLM team consists of 9 people spread between Veghel and Pune, India. The members are multi-disciplinary, including both technical and functional specialists. The PLM team is part of the ICT Platform and Technology Solutions department. This department focusses on delivery of services which are used for the development and lifecycle management of multi-disciplinary Vanderlande products. Required Skills & Competencies: Good knowledge of Enovia PLM (2016x onwards) Proficient in Core Java and JavaScript, JSP, Customization of UI3 Component, triggers, TCL Scripting, MQL. Knowledge of TVC (Technia Value Component) will be an added advantage. Experience in developing Web Services using SOAP and RESTFUL Services. Knowledge of Exalead search and its configuration. Knowledge of integration with Solidworks. Knowledge of build tools such as Ant, Gradle, or Maven. Experience with version control systems like GIT or Sourcetree. Experience in working with Eclipse/IntelliJ IDE. Understanding of Agile methodology and Scrum practices. Strong communication and interpersonal skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors - Electronics Engineering 4-8 Years hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. IR Signoff CPU/high performance cores Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs Development of PG Grid spec for different HM Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design Good knowledge on PD would is desirable. Python , Perl , TCL Skill Set Hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. Good understanding on Power Integrity Signoff Checks. Proficient in scripting languages (Tcl and Perl). Familiarity with Innovus for RDL / Bump Planning/PG eco . Ability to communicate effectively with multiple global cross-functional teams. Tools Redhawk , Redhawk_SC and basic use case of Innovus/ Fusion Compiler Power Planning/Floor planning ,Physical Verification hands on experience is added advantage. LSF /compute optimization understanding. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores . You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Experience 6 to 15 years of experience with good academics . Roles and Responsibilities Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency ( Python and TCL ). Knowledge of data structures and algorithms Experience with automation Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary Qualcomms Graphics PSE team is a part of the Graphics System team and is responsible for the overall quality of the Graphics IP in silicon. As a member of our Graphics PSE team, you will be working closely with architects, designers, verification, and software engineers to take the GPU from pre-Sil stage to tape out to silicon bring-up and to CS(Customer Samples). Job Functions/General Responsibilities In this position, you will be responsible for developing graphics applications using graphics API like DirectX, OpenGL ES , Vulkan, improving coverage, creating GPU bring-up test-plans and test methodologies. Analyzing and enabling new games and benchmark in pre-Si environment. Provide debug support in pre-Silicon environment (functional model) and driving end to end solutions for silicon bring-up issues including failure debug. We are looking for highly motivated engineers that enjoy working in a fast-paced environment with minimal guidance. Candidates must have strong programming, communication and teamwork skills and approach difficult challenges as learning opportunities. Critical "Must Have" skills/experience for role Strong programming in C/C++. GPU APIs knowledge (Vulkan/Direct3D/OpenGL/Direct X / OpenCL etc.) GPU architecture. Strong analytical skill. 4+ years of relevant experience. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 10+ years of Systems Engineering or related work experience.ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience.ORPhD in Engineering, Information Systems, Computer Science, or related field and 5+ year of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Preferred skills/experience for role Experience with at least one ofPerl, Python, TCL Games/graphics application development. OpenCL/CUDA knowledge. Graphics driver development or modelling experience. Post-silicon enablement and bring-up. Prior experience in working in emulation environments for development and debug. Debug tools including JTAG and kernel debuggers Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Preferred Qualifications: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 4+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 4+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.