1631 Tcl Jobs - Page 39

L&T Technology is looking to hire for Design Verification Engineers. Job Location : Bangalore Detailed JD is below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVNJob Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Show more Show less

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVN Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074279 Show more Show less

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance Job Description The position involves designing, developing and deploying UVM/C based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I3C, PWM. Responsibilities: Develop and track execution of chip level test planning to meet product requirements and established quality standards Lead a team to complete the pre-silicon verification of an SoC Execute and maintain chip level verification regressions. Triage and debug failing tests. Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification. Perform gate level verification across corners. Provide appropriate activity files for power analysis. Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure. Experience Level: 10-15 years in Industry Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage. Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Very strong Analytical debugging skills Knowledge on C Based Testcases. Knowledge of SoC,Memory and Cache Architectures Knowledge on Low power designs and architectures Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

Who We Are We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies, and improve lives. www.silabs.com About the team The IoT Digital Design team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide best in class technology solutions through innovation in custom RISC-V Cores and AI/ML components. What we’re looking for: Silicon Labs is seeking a Lead Engineer for the Emulation and Prototyping Platform (EPP) team. The position requires a thorough FPGA development and deployment background with focus on automation to efficiently deliver an emulation platform. Technical leadership and Mentorship experience preferred. Skills you’ll need: Deliver emulation platforms to internal groups to enable pre-silicon verification, validation, and software development. Provide hands-on technical leadership and training for staff. Schedule development, task assignment, and tracking to meet project milestones. Robust quality assurance metrics defined, documented, measured, and reported. Collaboration with internal teams and external vendors to define needs and set expectations. Identify and execute strategic initiatives to advance team delivery. Coordinate emulation and prototyping activities with a global engineering team. Communicates technical information and schedules to senior members of the management team. Functional Role: Worked with industry standard emulation and simulation tools. Ability to understand HDL language and understand HW/SW Codesign. Understand CDC, STA and other timing considerations in the context of FPGA. Advanced knowledge of clocking, memory and other FPGA needs. Experience with Lab equipment like Digital Signal Analyzer and Signal Generator. Knowledge of scripting languages like TCL, perl and python. Previous experience with Linux based version control environment (GIT, Perforce, Methodics). Worked with SystemVerilog and UVM testbench. Job Automation skills like Jenkins and Docker. Embedded C programming. PCB knowledge for schematic, layout, signal integrity consideration etc. Chip integration and bring-up experience. SW, Tooling and DevOps knowledge. Education and/or Experience: 6-8 years in Industry Bachelor or master’s degree in electrical and/or Computer Engineering Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability. Show more Show less

Responsibilities: * Ensure compliance with industry standards and customer requirements. * Design DFT solutions using ATPG, MBIST, Scan Insertion, JTAG tools.

Develop RTL (Verilog/SV) per microarchitecture specs, integrate IPs, perform lint/CDC, support synthesis. Strong in digital design, AMBA (AXI/AHB), low-power (UPF), TCL/Python. Tools: DC, Genus, SpyGlass. Collaborate on debug & reviews.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled & experienced engineer with SDC/RDC/CDC skills to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities: As part of the Design Enablement team of the organization, you need to collaborate with design and verification teams to implement robust CDC/RDC solutions into organization standard flows You will work with EDA Vendors to proactively review latest tools and flows offerings in this domain & evaluate latest offerings and benchmark with organization used tools, flows, and methodologies You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain 10+ Years of Experience Expertise in RTL Level checks understanding Expertise in CDC verification tools like Mentor Graphics Questa CDC and Synopsys SpyGlass CDC Expertise in utilizing tools like Synopsys Prime Time, Cadence Tempus, and Mentor Graphics for timing analysis Expertise in utilizing RDC verification tools and methodologies to identify and resolve reset-related issues. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can – do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments JD:- Asic RTL Design: Digital Design Knowledge RTL coding – System Verilog/Verilog/VHDL SoC integration experience is preferred CDC, Linting knowledge Synthesis, STA, DFT, Layout reviews experience Skills Rtl Coding,SOC integration,CDC Show more Show less

Facebook is hiring ASIC Design Engineers within our Infrastructure organization. We are looking for experienced individuals with knowledge that span one or more of the key areas required to build successful complex SoC and IP for data center applications. ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications: 15+ years of silicon development experience Track record of first-pass success in ASIC Development Experience with Verilog or System Verilog Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience working across multiple projects Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Preferred Qualifications: Experience in data path development Experience in CPU, NOC, Memory and Peripheral Subsystems Experience in HLS Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SOFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD’s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Minimum of 8 years of software design and development experience, preferably in a customer facing role Strong programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs in Linux environment Experience with software development in Real Time Operating Systems (RTOS – FreeRTOS, VxWorks, etc.) Experience with embedded processors such as ARM - debug/trace/AXI interconnect/Multicore-Processing/Cacheline/Instruction Pipeline/Interrupts/Timers Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA Experience in Software programming for FPGAs is an advantage Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Scripting language experience like Perl, Python or TCL is an advantage Effective communication and problem-solving skills Experience in successfully executing projects which require interaction with international sites and culturally diverse teams Experience in leading a software team is a plus ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent #LI-PS1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative Implementation & DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. This team encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain timing constraints in functional and DFT modes both at block and full chip level Work with Design and Physical Design teams to understand the violating paths and update constraints or provide guidance to Physical Design Engineers in solving DFT timing challenges Maintain or improve DFT clocking structures and IO budgets Create environment for validation of DFT structure consistency across design cycle and also check all possible ways to hit highest possible scan frequency targets Provide technical support to other teams PREFERRED EXPERIENCE: Good at Perl/TCL Scripting Familiarity with Synopsys SDC formats, Constraints analysis tools, constraints consistency checks tools Experience with analyzing and debugging post layout timing is a plus ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities: Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. (20%) Ensure the definition and implementation of test and verification plans. (20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification. (10%) Identify and resolve verification issues and bugs, ensuring timely project delivery. (10%) Continuously improve verification processes, methodologies, and tools. (10%) Manage project schedules, resources, and deliverables to meet deadlines. (10%) Oversee the writing and debugging of System Verilog assertion.(10%) Minimum Qualifications: 8+ years of relevant experience in SOC verification. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g., VCS, Questa Sim). Experience with SoC design verification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles And Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred Qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074404 Show more Show less

Alternate Job Titles: Senior Analog Design Engineer Senior SERDES Engineer Senior Mixed-Signal Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated Analog Design Engineer with a passion for developing high-speed analog integrated circuits. You thrive in a collaborative environment and enjoy working with cross-functional teams to achieve design success. You possess a deep understanding of transistor-level circuit design and have hands-on experience with SERDES IP development. Your expertise in CMOS design fundamentals and familiarity with SERDES sub-circuits, such as TX, RX, adaptive equalizers, PLL, DLL, ADC, BGR, and regulators, makes you an ideal candidate for this role. You are aware of ESD issues and have a sound knowledge of custom digital design, design for reliability, and layout effects. You are proficient in using custom design tools and have experience with scripting for post-processing simulation results. Your excellent communication and documentation skills enable you to effectively convey complex technical information to various stakeholders. What You’ll Be Doing: Designing, developing, troubleshooting, and debugging multi-Gb/s SERDES IP. Working from SerDes standards to block specifications to identify potential circuit architectures and successful design strategies. Collaborating with a cross-functional design team of analog and digital designers from diverse backgrounds. Utilizing a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. Ensuring designs meet performance, reliability, and manufacturability requirements. Documenting design processes and results for knowledge sharing and future reference. The Impact You Will Have: Contributing to the development of cutting-edge high-speed analog integrated circuits. Enhancing the performance and reliability of SERDES IP used in various high-tech applications. Driving innovation in analog and mixed-signal design methodologies. Collaborating with a talented team to deliver world-class design solutions. Supporting the growth and success of Synopsys' analog and mixed-signal R&D initiatives. Ensuring the seamless integration of analog and digital components in complex systems. What You’ll Need: In-depth familiarity with transistor-level circuit design and CMOS design fundamentals. Exposure to SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, ADC, BGR, regulators). Awareness of ESD issues and circuit techniques for mitigation. Familiarity with custom digital design for high-speed logic paths. Knowledge of design for reliability (e.g., EM, IR, aging) and layout effects (e.g., matching, reliability, proximity effects). Proficiency with custom design tools such as Cadence, HSPICE, HSIM, and Ultrasim. Experience with scripting languages for post-processing simulation results (e.g., TCL, PERL, MATLAB). Understanding of system-level budgeting for jitter, amplitude, noise, etc. Awareness of signal integrity issues, including packaging effects, board parasitics, crosstalk, and noise. Who You Are: A collaborative team player who excels in a cross-functional environment. A problem solver with strong analytical skills and attention to detail. An effective communicator with excellent documentation skills. A self-motivated individual with a passion for continuous learning and innovation. Adaptable and able to thrive in a fast-paced, dynamic work environment. The Team You’ll Be A Part Of: You will be part of a fast-growing analog and mixed-signal R&D team dedicated to developing high-speed analog integrated circuits. Our team consists of talented analog and digital designers from diverse backgrounds, working collaboratively to achieve design excellence. We leverage a best-in-class environment with a comprehensive suite of IC design tools, supported by an experienced software/CAD team, to drive innovation and deliver cutting-edge solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Description & Requirements At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Solution IP group in Boxborough, Massachusetts is ramping up high-performance computing (HPC) demand, therefore we are looking for an enthusiastic engineer to join our Analog & Mixed-Signal Circuit Design & Methodology team. You will be working with an immensely creative cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience and working knowledge of mixed signal circuit design best practices, an understanding of silicon IP release requirements, solid scripting skills to automate flows and the ability to drive and train engineers to become experts with new methodologies. Job Responsibilities: Review SerDes standards and architecture documents to develop analog sub-block specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Required Qualifications: Bachelor with 4 years' experience or MSEE (or PhD) with 2 years' experience in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control/data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++ Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated individual with a passion for technological innovation and continuous improvement. You thrive in a fast-paced environment and are eager to contribute to cutting-edge projects. You possess a solid engineering understanding of the underlying concepts of IC design and have strong knowledge of the full design cycle from RTL to GDSII, including the development of timing constraints. Your expertise in the implementation flows and methodologies for deep sub-micron designs is unparalleled. You have experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution. You have a proven track record of contributing to project tape-outs and are proficient in timing closure and signal integrity. Your software and scripting skills (Perl, Tcl, Python) are top-notch, and you have knowledge of CAD automation methods. You are a team player who can interface with the larger product team to understand design constraints, deliverable formats, and customer requirements. With at least 3 years of physical design experience, you have hands-on experience with the design of complex ASSP and COT designs and are familiar with Synopsys tools, flows, and methodologies. What You’ll Be Doing: Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have: Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate with cross-functional teams to meet customer requirements What You’ll Need: Solid engineering understanding of IC design concepts Strong knowledge of the full design cycle from RTL to GDSII Expertise in implementation flows and methodologies for deep sub-micron designs Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution Proven experience with project tape-outs and timing closure Proficiency in software and scripting skills (Perl, Tcl, Python) Knowledge of Synopsys tools, flows, and methodologies Who You Are: You are a detail-oriented, innovative thinker with excellent problem-solving skills. You have a collaborative mindset and can work effectively in a team-oriented environment. Your strong communication skills enable you to convey complex technical concepts clearly. You are adaptable, continuously seeking to improve your skills and knowledge. You are dedicated to delivering high-quality results and are motivated by the opportunity to work on cutting-edge technology. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on physical design and implementation. Our team is dedicated to pushing the boundaries of technology and innovation. We work collaboratively to solve complex design challenges and deliver high-performance solutions. Joining our team means being part of a supportive environment where your contributions are valued, and your growth is encouraged. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076511 Show more Show less

Job Title: IP Logic Design Engineer (Mid to Senior Level) Location: Bengaluru, India Experience: 7–15 years Industry: Semiconductors | AI | Networking | ASIC Design Job Type: Full-time About the Role:- We are seeking a highly motivated and experienced IP Logic Design Engineer to join our growing team in Bengaluru . As a key member of our hardware design team, you will be responsible for defining, implementing, and verifying complex RTL blocks used in cutting-edge ASICs for networking and AI applications. Key Responsibilities · Develop detailed micro-architecture specifications and actively contribute to technical reviews. · Design and implement RTL for complex functional blocks, ensuring compliance with functionality, timing, performance, and power targets. · Collaborate on IP modules such as FIFO, cache, queue managers, schedulers, packet processors, MAC, and other networking blocks. · Partner with verification teams to debug design issues, enhance functional/code coverage, and support testbench development. · Execute front-end design tasks including linting, CDC (Clock Domain Crossing) analysis, and formal property verification. · Support backend teams with synthesis, timing analysis, timing closure, and contribute to floor planning and ECOs (Engineering Change Orders). Key Skills & Experience:- · Strong proficiency in RTL design and micro-architecture for networking and high-performance systems. · Deep understanding of Ethernet switch/router, Network Interface Card (NIC), and related IP architectures. · Hands-on experience with industry-standard front-end design tools and methodologies. · Familiarity with scripting languages such as Python, Perl, TCL for design automation and workflow optimization. Job Types: Full-time, Permanent Pay: ₹372,700.40 - ₹4,000,000.00 per year Benefits: Health insurance Paid time off Provident Fund Schedule: Day shift Morning shift Ability to commute/relocate: Bengaluru, Karnataka: Reliably commute or planning to relocate before starting work (Required) Location: Bengaluru, Karnataka (Preferred) Work Location: In person Application Deadline: 23/06/2025

Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. Arista is a well-established and profitable company with over $7 billion in revenue. Arista’s award-winning platforms, ranging in Ethernet speeds up to 800G bits per second, redefine scalability, agility, and resilience. Arista is a founding member of the Ultra Ethernet consortium. We have shipped over 20 million cloud networking ports worldwide with CloudVision and EOS, an advanced network operating system. Arista is committed to open standards, and its products are available worldwide directly and through partners. At Arista, we value the diversity of thought and perspectives each employee brings. We believe fostering an inclusive environment where individuals from various backgrounds and experiences feel welcome is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as the Great Place to Work Survey for Best Engineering Team and Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest quality and performance standards in everything we do. Job Description Candidates for this position would be responsible for the entire unit software design process: Authoring stress tests to validate hardware conceptual designs Authoring Functional Specifications to communicate intentions with the broader team Debugging of challenging issues multi-server execution environments Reviewing peers’ code against good-practices and target architectures Unit-test code development for validation (positive and negative testing) or new tests created Development of doc templates and test reports to communicate with hardware team counterparts of testing results Root-cause unexpected issues and develop multi-layered patches to address immediate and long-term consequences of the issue Drive your own efforts to contribute to hardware tools team overall priorities Learn the varied code languages to support the various tools used by existing team development software suites, including C/C++, golang, python, TCL, and others. Qualifications B.S. Electrical Engineering and/or B.S. Computer Engineering 3-5 years of relevant experience in software engineering for tools development Self-motivated w/ a passion for developing “elegant”, high-quality software solutions A strong curiosity supporting continuous learning and self-development Great communication skills and team-driven mindset Experience working with large software ecosystems utilizing CI/CD workflows Knowledge working with multi-processor clusters and computing environments Fundamental knowledge of networking protocols and operation Enthusiasm to work collaboratively with a multidisciplinary team to achieve a greater overall solution. Show more Show less

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

Key Responsibilities: Perform high-quality mesh generation for structural analysis using Hypermesh and Patran . Develop and refine GFEM and DFEM models for various components and assemblies, ensuring mesh quality and compliance with CAE standards. Prepare models for static, dynamic, and thermal FEA simulations. Interpret and apply engineering drawings and CAD data to build accurate finite element models. Ensure mesh quality and convergence to meet analysis requirements. Ensure adherence to customer-specific FEM guidelines and industry best practices. Collaborate closely with design, simulation, and test teams to validate and iterate FE models. Document meshing processes, model assumptions, and preprocessing methodologies. Troubleshoot and resolve issues related to meshing and model setup. Familiarity with optimization techniques for FE modeling. Required Skills & Qualifications: Bachelor's or Master's degree in Mechanical, Aerospace, or related engineering field. 3 to 7 years of relevant CAE experience , with a focus on meshing and preprocessing. Strong command of Hypermesh and Patran for shell and solid meshing. Hands-on experience in GFEM and DFEM meshing techniques and standards. Solid understanding of FEA fundamentals, material properties, and boundary conditions. Familiarity with CAD software (e.g., CATIA, NX) for model extraction and cleanup. Excellent problem-solving and communication skills. Ability to manage multiple tasks and meet tight deadlines. Proactive attitude towards continuous improvement and learning. Preferred: Exposure to solver environments like OPTISTRUCT , NASTRAN , ABAQUS for FE model set-up Experience with scripting or automation (e.g., TCL, Python) in preprocessing. Knowledge of aerospace or automotive domain-specific CAE workflows.