934 Tcl Jobs - Page 38

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes ENOVIA V5 Good to have skills : No Function Specialty Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. You will oversee the development process and ensure successful implementation of applications. Roles & Responsibilities:1.Capable of understanding and contributing to the technical solution from 3DEXPERIENCE design through code level.2. Capable of providing solutions & mentoring support to the team.3.Taking ownership of individual tasks (implementation and bug fixing) and ensuring the delivery of assignments on-time with quality. Extending Support to the team when required4.Awareness and adherence to the best practices to the coding standards of Enovia API/EKL/CAA. Professional & Technical Skills:1. Must have skills- 3DExperience/CATIA/Enovia - Customization2. Experience with 3DExperience Enovia customization, configuration and SME role.3. Excellent verbal and written communication skills. Additional Information:1. The candidate should have a minimum of 4+ years of experience in 3DExperience/CATIA/Enovia - Customization.2. Should be a team player.3. This position is based at our Bengaluru office. Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes 3DEXPERIENCE ENOVIA Customization Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process and ensuring seamless communication within the team and stakeholders. Roles & Responsibilities:1. Develop automated test scripts using automated tools such as Eggplant , UFT ,Selenium for Web and mobile applications.2. Experience in Functional Manual Testing of DS ENOVIA or CATIA or DELMIA3. Must know 3DExperience 2016X and above. Must know basic of Enovia Functional. Basic understanding of 3DExperience Architecture , Component and MQL. 4. Expected to be an SME, collaborate and manage the team to perform. Responsible for team decisions. -5. Engage with multiple teams and contribute on key decisions. 6. Expected to provide solutions to problems that apply across multiple teams. 7. Lead and manage the testing team to ensure the successful implementation of automation testing strategies. 8. Develop and maintain automated test scripts and frameworks. 9. Design and execute test plans, test cases, and test scripts. -10. Identify and report defects and issues in a timely manner. -11. Collaborate with cross-functional teams to ensure the delivery of high-quality software products. Professional & Technical Skills:1.Must know Implementation knowledge of Eggplant Tool.2.Solid knowledge of programming languages such as Java or Python. 3.Familiarity with CI/CD pipelines and DevOps practices. Additional Information:1. Must have 7+ years of experience in Eggplant , 3DExperience 3DExperience/Enovia2. Outstanding all-round communication skills and ability to work collaboratively 3. Team player and work closely with other peers Qualifications 15 years full time education

responsibilities The Network Engineer role includes the following responsibilities: Receive and manage escalations from other teams as well as various monitoring tools involving service-affecting issues. Troubleshoot, isolate and correct service-affecting issues on the network in areas including but not limited to:routing protocols, routers, switches, firewall administration, MPLS, BGP, VPN, load balancing. Plan, schedule, and implement network maintenance activities which include software upgrades, hardware replacement and network infrastructure augments/changes. As needed, implement approved routing policy changes/corrections to mitigate points of traffic congestion on the network due to planned or unplanned incidents. Work with network infrastructure/service providers to identify and correct causes of circuit disruption. Work with hardware vendors to determine causes of device failure/issues. Create network connectivity diagrams and other documentation of live network environments for internal and customer use. Incident management during critical events that impact the network, including internal and external communications, team coordination of repair and then root cause analysis efforts. Performance analysis and optimization Create diagrams and other documentation of network environments Communicate effectively with internal and external audiences with varying levels of technical expertise. Maintains high quality customer service to internal and external groups when needed. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2+ years of experience. Working knowledge of the following network protocols/technologies: BGP, MPLS, OSPF and related protocols Link aggregation protocols Dark fiber / DWDM systems Other skills: High Availability Technologies:HSRP, VRRP, MLAG, VSS, VPC Scripting Languages:Python, Perl, Bash, Expect/TCL Operating Systems:Linux, BSD Advanced Configuration of Arista, Juniper and Cisco devices Strong troubleshooting experience Preferred technical and professional experience Demonstrated history of organization and time management skills Demonstrated history of verbal and written communication skills Ability to work remotely with little or no direct supervision Exhibit a strong understanding of customer service Must be self-motivated and disciplined Ability to recognize and prioritize critical tasks independently Vendor Certifications:JNCIE, JNCIP, CCNP, CCDP, CCIE Vendor Hardware Platforms:Arista Switches, Cisco Nexus, Juniper MX

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071188

Role Description Role Proficiency: Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineersEnsure quality delivery as approved by the senior engineer or project lead Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Outputs Expected Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top levelEnsure functional spec / design guidelines are met 100% of the time without deviation or limitationDocumentation of the tasks and work performed Timely Delivery Meet project timelines as given by the team lead/program managerHelp with intermediate tasks delivery by other team members to ensure progress Teamwork Teamwork participation; supporting team members in the time of needAble to perform additional tasks in case of any team member(s) is not available Innovation & Creativity Pro-actively plan approach towards repeated work by automating tasks to save design cycle timeParticipation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Required technical skills and prior design knowledge to execute assigned tasks Ability to learn new skills in case required technical skills are not present to a level needed to execute the project Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT Strong communication skillsGood analytical reasoning and problem-solving skills with attention to detail Knowledge Examples Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Good Understanding of the design flow and methodologies used in designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set Additional Comments Required Primary Key skills – STA, nano time Job Description: You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting-edge technologies. You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs. You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for Lower tech node ( Below 14nm) Desired Skills and Experience: B. Tech. / M. Tech. with 2-8 years of experience in Synthesis, STA Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains Worked on pre and post layout timing analysis and resolving the issues Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...) Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nmGood knowledge of EDA tools from RC, DC, PT, PTSI Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Good knowledge of VLSI process and device characteristics Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting Skills Vlsi,Tlc,Perl

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products.Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler.Working with Verilog and VCS to ensure design accuracy.Defining synthesis design constraints and resolving STA issues.Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry.Enhancing the performance, power, and size efficiency of our silicon IP offerings.Enabling rapid market entry for differentiated products with reduced risk.Driving innovation in high-speed digital design and data recovery circuits.Supporting the creation of high-performance silicon chips and software content.Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.Proficiency in running lint/cdc/rdc checks and synthesis flow.Experience in coding, verifying Verilog and System Verilog design.Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC.Experience of leading technically for front-end activities.Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams.Self-motivated and proactive, with a strong attention to detail.A creative problem-solver who can think independently.Capable of working under tight deadlines while maintaining high-quality standards.A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys is seeking a creative, ambitious, and talented engineer to fill a full-time Analog CAD Support Engineer position in Noida/Bengaluru/Hyderabad/Pune. This role offers stimulating, challenging, and rewarding work within an excellent environment, providing positive career development opportunities. We are looking for someone who excels in teamwork, understands requirements, and thinks creatively to find solutions. While following established procedures is crucial, having a critical perspective and making informed decisions daily is equally important. The ideal candidate will be responsible and passionate about supporting R&D and improving the design process through automation to enhance quality and productivity. Responsibilities: Enable, support, and debug transistor-level flows and processes.Design, develop, troubleshoot, and debug software tools and flows for the development of integrated circuits.Support a global design team, debug CAD issues, interface with foundries, configure the CAD environment, and design flows.Develop routines and utility programs to aid in the design of integrated circuits.Build productive internal and external working relationships. Requirements: A relevant degree in electronic/microelectronic engineering.5+ years of relevant experience.Strong desire to learn and explore new technologies, demonstrating good analysis and problem-solving skills.Ability to exercise judgment within defined procedures and practices to determine appropriate action.Good knowledge of hardware integrated circuits.UNIX/Linux user knowledge.Proficiency with at least one programming language.Proficiency with scripting languages to automate processes.Good English communication skills.Capability to produce adequate technical documentation. Preferred Qualifications: Experience with the VLSI domain, including familiarity with DRC/LVS extraction, simulation, and EMIR.Experience with Cadence, Custom Designer EDA tools.Experience in data management and job scheduling tools like LSF/GRID Engine.Experience in Python, TCL, or Shell scripting.IC design experience (analog or digital). We design and verify advanced silicon chips for our customers. Our goal is to build faster chips, and we are the best in the world at doing so. We also create the processes and models necessary to manufacture these chips. By working with us, our customers can improve their chips in terms of power, cost, and performance, saving time by shortening their project schedules. At Synopsys, we are involved in groundbreaking technologies that shape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. As a company, we lead the way in developing advanced chip design and software security technologies that power these innovations. If you are passionate about innovation like we are, we would love to meet you. We value inclusion and diversity. At Synopsys, we treat all job applicants equally, regardless of their race, color, religion, nationality, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Description & Requirements At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Solution IP group is ramping up high-performance computing (HPC) demand, therefore we are looking for an enthusiastic engineer to join our Methodology and Analog & Mixed-Signal Circuit Design team. You will be working with an immensely creative cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience and working knowledge of mixed signal circuit design best practices, an understanding of silicon IP release requirements, solid scripting skills to automate flows and the ability to drive and train engineers to become experts with new methodologies. Job Responsibilities: Develop and maintain circuit design methodology flows and documentation.Identify and refine circuit implementations to achieve optimal power, area and performance targets.Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.Oversee physical layout to minimize the effect of parasitic, device stress, and process variation.Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.Present simulation data for peer and customer review.Mentor and Review the progress of junior engineers.Document design features and test plans. Required Qualifications: Bachelor with 2 years' experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical fieldIn-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.Silicon-proven experience implementing circuits like bandgap references, voltage regulators.Detailed design experience with high custom logic designExperience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).Experience with EDA tools for schematic entry, physical layout, and design verification.High proficiency with spice simulators including HSPICE, Finesim and XAKnowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control/data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-afterExperience with STA and cell characterization such as Nanotime, Primetime, SiliconSmartExperienced in STAR or similar extractor to debug extraction issuesExtensive programming skills in languages such as Python, Perl, TCL and C/C++

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063953