1597 Tcl Jobs - Page 37

Job Details Job Description: Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, discussions with customers, design reviews Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation Define, create and maintain all project related documentation, especially design documents with detailed analysis reports Provide support to customer during integration phases at test sites and support to production teams Qualifications Qualification Required: Bachelor's or Master's degree in Computer Science, Engineering in Electronics or Electrical or Telecom or VLSI Engineering or equivalent practical experience Requires minimum of 5+ years of experience in FPGA designs all the way from requirements to micro-architecture to implementation to debug and bringup on Hardware Preferred to have system level understanding Proficiency with System Verilog and RTL coding skills, timing closure, or STA, targeting high performance designs Very good understanding of latest protocol specifications for memory, bus protocol specification like AXI, PCIe and Ethernet interfaces, Security IPs (for ex: MACSec) Experience with FPGA tools and timing closure Hardware power-on and debug New product release and rollout support Customer technical support Good communication and presentation skills. Required Technical And Professional Expertise FPGA Design : Verilog/System Verilog RTL Coding FPGA Synthesis & Place&Router/Fitter Tools Functional Simulation Hardware Design : Logic Design & Debugging expertise Version control tools like Git Experience with scripting languages (Python, Perl, TCL, Bash, etc.) Job Type Regular Shift Shift 1 (India) Primary Location: Ecospace 1 Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Summary We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design Responsibilities : Design and implement scalable RTL architectures for complex SoC components using Verilog/SystemVerilog. Develop and maintain logic blocks aligned with architectural and functional specifications. Collaborate with design verification and architecture teams to define module interfaces and performance metrics. Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc. Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms. Analyze design performance and optimize RTL for area, power, and logical efficiency. Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards. Simulate and debug logic design using industry tools and waveform analysis. Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting Skills & Experience : 5+ years of experience in RTL design, logic development, and micro-architecture. Strong command over Verilog/SystemVerilog and digital design methodologies. Proven experience in designing software-driven SoC architectures with modular, configurable RTL. In-depth knowledge of AMBA protocols - AXI, AHB, APB. Experience in multi-clock domain logic and asynchronous interface design. Proficiency in low-power RTL techniques including power-aware coding and UPF/CPF flows (logic-level). Familiarity with RTL design tools such as Simulation (ModelSim/VCS), Linting, CDC/RDC tools. Scripting skills in TCL, Python, or Shell for automating RTL testbenches, configuration, or IP Qualifications : Bachelors or Masters degree in, Computer Engineering, or related field. Exposure to software-based SoC modeling or transaction-level modeling (TLM). Experience with design abstraction, reusable IP architecture, and configurable RTL components. Knowledge of interfaces such as USB, PCIe, SD/eMMC at RTL level. (ref:hirist.tech)

Responsibilities : About Lexmark: Founded in 1991 and headquartered in Lexington, Kentucky, Lexmark is recognized as a global leader in print hardware, service, software solutions and security by many of the technology industry’s leading market analyst firms. Lexmark creates cloud-enabled imaging and IoT solutions that help customers in more than 170 countries worldwide quickly realize business outcomes. Lexmark’s digital transformation objectives accelerate business transformation, turning information into insights, data into decisions, and analytics into action. Lexmark India, located in Kolkata, is one of the research and development centers of Lexmark International Inc. The India team works on cutting-edge technologies & domains like cloud, AI/ML, Data science, IoT, Cyber security on creating innovative solutions for our customers and helping them minimize the cost and IT burden in providing a secure, reliable, and productive print and imaging environment. At our core, we are a technology company – deeply committed to building our own R&D capabilities, leveraging emerging technologies and partnerships to bring together a library of intellectual property that can add value to our customer's business. Caring for our communities and creating growth opportunities by investing in talent are woven into our culture. It’s how we care, grow, and win together. Experience: 2 to 10 years Job Description: You will be part of the ENOVIA Development Team and can independently develop solutions on ENOVIA to provide technical solutions. Key Responsibilities: You will be part of the ENOVIA Development Team dedicated to offering highly scalable, best-in-class technical solutions. Provide technical expertise in identifying, evaluating, and developing technology solutions on ENOVIA & adjacent Enterprise Integrations. Participate in all phases of SDLC including requirement analysis, solution design, configuration/development, code review, and support deployment & Testing activities. Skill Requirements: Educational background - BE/ME/MCA Professional experience: 2 to 10 Years of professional experience in implementing PLM solutions using 3DEXPERIENCE ENOVIA/V6. Hands-on experience in Enovia Customization and Defect Fixing. Experience working with ENOVIA Roles/Apps: Engineering BOM Management, Material Compliance (MCC), Variant Management, Classify and Reuse, etc. Hands-on expertise on Enovia Tools/Utilities: ENOVIA ADK, MQL, TCL/TK, UI3 Components, developing JPO and Triggers, and REST-based Webservices. Experience in Core Java, J2EE, JSP, Servlets, JavaScript, and jQuery. Experience in Technia Value Components (TVC), Enovia integrations, and the latest versions of 3DEXPERIENCE ENOVIA (2018x - 2023x) would be an added advantage. Strong verbal and communication skills. How to Apply ? Are you an innovator? Here is your chance to make your mark with a global technology leader. Apply now! Global Privacy Notice Lexmark is committed to appropriately protecting and managing any personal information you share with us. Click here to view Lexmark's Privacy Notice.

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known, To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way, About the Job:. Juniper Network’s Security Incident Response Team (SIRT) is the focal point for discovering and remediating product security vulnerabilities. The role of an Incident Manager (IM) is to drive security defects to resolution by understanding the software flaw, its impact, its proper resolution, and then communicating that to customers through Juniper Security Advisories. SIRT IMs are part of a global team that works closely with both the support and engineering organizations. The role requires understanding of secure software development and the consequences of security flaws. The successful candidate will have a passion for security and an ability to see problems with a security professional’s perspective, Responsibilities:. Juniper is seeking an experienced Security Incident Response Manager to join the Juniper SIRT, The SIRT IM is responsible for:. Investigating reports of potential vulnerabilities. Analyzing software flaws and working with engineering teams to ensure proper remediation. Authoring and presenting Security Advisories. Working with external security communities, security researchers, and customers. Managing the response to product security incidents. Requirements:. Should have 2-4 years of product security incident response experience, Familiarity with secure programming concepts and testing, Good understanding of web application security threats and defenses (SQL Injection, XSS, CSRF, etc,,), Good understanding of database security threats and defenses (cloud/container configuration, access control, authentication, misconfigured and abused privileges, logging and auditing), Familiarity with OWASP guidelines. Participation in a local OWASP chapter or similar security focused communities is a plus, Familiarity with Common Vulnerabilities and Exposure (CVE) systems, Coordinated Vulnerability Disclosure (CVD), Familiarity with the Common Weakness Enumeration (CWE) types and CERT Secure Coding Standards, Familiarity with the Common Vulnerability Scoring System (CVSS), Familiarity with agile software development/continuous integration/automation, Minimum of a Bachelor’s Degree in Engineering or Computer Science or Cybersecurity or similar, Excellent written and verbal communication skills. Should be able to produce a writing sample: A blog entry or other long-form post on a technical issue, comment on a mailing list or open source issue or other technical comment on social media, a self-written academic paper, Strong analytical and problem-solving skills, and the ability to work independently, Ability to collaborate across functional teams as well as external partners, researchers, and other security teams, Ability to track multiple issues in various states of progress, Desired Qualifications:. A strong ability to use scripting languages such as Perl, Python, TCL, and UNIX shell programming, Demonstrated experience (such as academic projects) in JavaScript, NodeDot js, Pug, PHP, Python, Java, C/C++, R, Rust, relational and NoSQL databases, Experience with HTML, CSS, JSON, XML file creation and management. Experience with AWS, Azure, GCP, Snowflake, Should be able to produce a sample code such as a project hosted on GitHub or personal site, Linux and/or FreeBSD experience along with the ability to read and understand multiple programming languages, Familiarity with routing and switching protocols and security firewalls, About Juniper Networks. Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www,juniperDot Net) or connect with Juniper on Twitter, LinkedIn and Facebook, WHERE WILL YOU DO YOUR BEST WORK?. Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job it's an opportunity to help change the world, At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you, Additional Information for United States jobs:. ELIGIBILITY TO WORK AND E-VERIFY. In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire, Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers, Information for applicants about E-Verify / E-Verify Informacin en espaol: This Company Participates in E-Verify / Este Empleador Participa en E-Verify. Immigrant and Employee Rights Section (IER) The Right to Work / El Derecho a Trabajar. E-Verify® is a registered trademark of the U.S. Department of Homeland Security, Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need, Show more Show less

Job Description We are looking for a highly skilled Senior Data Engineer / BI Consultant with 7+ years of experience in implementing commercial projects across Data Engineering, Business Intelligence, ETL, and Data Warehousing. The ideal candidate will have strong hands-on expertise in SQL, ETL tools, BI platforms, and modern database environments. Responsibilities Lead end-to-end implementation of data projects in enterprise environments. Design and develop robust and scalable ETL pipelines using industry-leading ETL tools. Analyze business requirements and translate them into technical solutions using data models and visualizations. Develop and manage reporting dashboards using BI tools like SAP Analytics Cloud, Power BI, Tableau, or Qlik. Work with relational and columnar databases (e.g., Oracle, SAP BW, Teradata, Exasol) for efficient data processing. Write optimized SQL for data extraction, transformation, and reporting purposes. Collaborate with stakeholders to ensure timely delivery and effective business insights. Implement data governance, metadata management, and security protocols in reporting and data warehousing. Perform unit testing, peer reviews, and performance optimization of ETL and BI solutions. Required Experience And Qualifications 7+ years of hands-on experience in data engineering, BI, or data science projects. Proficiency in SQL: including DML, DDL, DCL, and TCL operations. Experience in BI tools: such as SAP Analytics Cloud, Tableau, Power BI, Qlik, or MicroStrategy. ETL/Data Integration tools expertise: Informatica, Dataiku, Oracle Data Integrator, Talend, Pentaho DI, or IBM DataStage. Strong knowledge of data warehousing platforms: Oracle, Teradata, SAP BW, or Exasol. Ability to work independently and manage multiple priorities in a fast-paced environment. Solid understanding of data modeling, performance tuning, and data lifecycle management. Preferred Skills Knowledge of cloud platforms (AWS, Azure, GCP) and integration with data/BI solutions. Familiarity with big data technologies (Spark, Hive, HDFS) is a plus. Understanding of DevOps practices and CI/CD in data project delivery. Experience with version control tools like Git. Skills: etl,qlik,talend,oracle data integrator,bi platforms,exasol,hive,devops practices,pentaho di,ibm datastage,ci/cd,aws,performance tuning,informatica,tableau,power bi,data lifecycle management,git,data modeling,hdfs,teradata,sql,etl tools,dataiku,oracle,gcp,azure,data warehousing,spark,sap analytics cloud,sap bw

Responsibilities : About Lexmark: Founded in 1991 and headquartered in Lexington, Kentucky, Lexmark is recognized as a global leader in print hardware, service, software solutions and security by many of the technology industry’s leading market analyst firms. Lexmark creates cloud-enabled imaging and IoT solutions that help customers in more than 170 countries worldwide quickly realize business outcomes. Lexmark’s digital transformation objectives accelerate business transformation, turning information into insights, data into decisions, and analytics into action. Lexmark India, located in Kolkata, is one of the research and development centers of Lexmark International Inc. The India team works on cutting-edge technologies & domains like cloud, AI/ML, Data science, IoT, Cyber security on creating innovative solutions for our customers and helping them minimize the cost and IT burden in providing a secure, reliable, and productive print and imaging environment. At our core, we are a technology company – deeply committed to building our own R&D capabilities, leveraging emerging technologies and partnerships to bring together a library of intellectual property that can add value to our customer's business. Caring for our communities and creating growth opportunities by investing in talent are woven into our culture. It’s how we care, grow, and win together. Experience: 2 to 10 years Job Description: You will be part of the ENOVIA Development Team and can independently develop solutions on ENOVIA to provide technical solutions. Key Responsibilities: You will be part of the ENOVIA Development Team dedicated to offering highly scalable, best-in-class technical solutions. Provide technical expertise in identifying, evaluating, and developing technology solutions on ENOVIA & adjacent Enterprise Integrations. Participate in all phases of SDLC including requirement analysis, solution design, configuration/development, code review, and support deployment & Testing activities. Skill Requirements: Educational background - BE/ME/MCA Professional experience: 2 to 10 Years of professional experience in implementing PLM solutions using 3DEXPERIENCE ENOVIA/V6. Hands-on experience in Enovia Customization and Defect Fixing. Experience working with ENOVIA Roles/Apps: Engineering BOM Management, Material Compliance (MCC), Variant Management, Classify and Reuse, etc. Hands-on expertise on Enovia Tools/Utilities: ENOVIA ADK, MQL, TCL/TK, UI3 Components, developing JPO and Triggers, and REST-based Webservices. Experience in Core Java, J2EE, JSP, Servlets, JavaScript, and jQuery. Experience in Technia Value Components (TVC), Enovia integrations, and the latest versions of 3DEXPERIENCE ENOVIA (2018x - 2023x) would be an added advantage. Strong verbal and communication skills. How to Apply ? Are you an innovator? Here is your chance to make your mark with a global technology leader. Apply now!

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Job Description We are seeking a meticulous and skilled CAE Modeling Engineer to join our CAE team. In this role, you will be instrumental in the pre-processing phase of Finite Element Method (FEM) for vehicle Body-in-White and full vehicle models, focusing on Durability and NVH performance. You will be responsible for handling, validating, and preparing complex engineering data, CAD and BOM, to create high-quality FE models for analysis. This position requires a strong understanding of FE modeling best practices, excellent data handling skills, and the ability to communicate effectively with the modeling team. Responsibilities Perform detailed studies and checks on incoming CAD data, identifying missing geometry, evaluating data quality issues, and resolving geometric intersections that would impact FE model integrity. Develop and execute queries to extract, process, and verify critical input data from various sources, including CAD, Bill of Materials, Non-Geometric Data, connection lists, and other relevant engineering databases. Act as a technical liaison, providing clear direction, feedback, and necessary clarifications to the core FE modeling team regarding data issues, model requirements, and preparation methodologies. Apply relevant BOM information, material properties, boundary conditions, and other applicable FE mechanisms and attributes within the Body Durability and NVH FE models. Prepare and define complex system model connections and assemblies, accurately representing physical joining methods such as spot welds, seam welds, adhesives, bolts, springs, and other fasteners within the FE model. Execute geometry clean-up procedures, including performing de-penetration and resolving intersections both within individual component models and across complex system assemblies. Rigorously review Body Durability and NVH FE models against standard checklists, guidelines, and best practices to ensure accuracy, completeness, and adherence to modeling standards. Identify, diagnose, and effectively debug and fix errors, warnings, and inconsistencies within the FE models to ensure they are robust and ready for successful analysis runs. Qualifications Required skills Bachelor's degree in Mechanical Engineering, Automotive Engineering, or a related technical field. 3+ years of experience in CAE pre-processing, FE modeling, or engineering data preparation, preferably within the automotive industry. Proficiency with major FE pre-processing software (e.g., HyperMesh, ANSA). Experience handling and validating large CAD assemblies and complex geometric data. Strong understanding of engineering data sources such as BOMs, material specifications, and fastening standards. Solid knowledge of FE modeling principles, especially regarding the accurate representation of various connection types (welds, bolts, adhesives, etc.). Familiarity with Body-in-White or full vehicle structural components and assemblies. Ability to read and interpret engineering drawings, specifications, and technical documentation. Excellent attention to detail and a systematic approach to data verification and model quality checks. Good verbal and written communication skills for providing technical direction and clarifications. Good to have skills - Experience with specific CAD software (e.g., CATIA, 3DX or NX). Familiar with CAE solvers like Nastran, Abaqus or LS-DYNA. Experience with scripting languages (e.g., Tcl, Python) for automation of pre-processing tasks. Knowledge of Product Lifecycle Management systems (Enovia or Teamcenter). Basic understanding of Durability or NVH analysis principles.

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures.

Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 7/10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 7/ 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle7 Experience with verification of ARM/RISC-V based CPU sub-systems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control systems like Mercurial(Hg), Git or SVN

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. More About Silicon Labs We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company. The Role Silicon Labs is building a world class Software Centre of Excellence in the best office space in Hyderabad. We are looking for an experienced Software Quality Assurance (SQA) Engineer for the Multi-Protocol team as an Associate Staff Engineer. Our Hyderabad SQA team is focused on improving the overall quality of software used in Silicon Labs Wi-Fi /BT/BLE/15.4 combo chips targeting Internet of Things(IoT), Wearables & Industrial Automation applications. This position is based out of Silicon Labs, Hyderabad. What you will do: Take technical ownership of SQA activities for Silicon Labs’ IoT Product offering, ensuring high-quality deliverables. Collaborate closely with SQA team members to drive the successful delivery of projects as per commitments. Demonstrate a proactive, can-do attitude and contribute to a positive team environment. Lead by example in tracking and progressing automation of new features, while also addressing legacy backlog items. Present project progress and technical insights to local and global leadership as required. The ideal candidate has commercialization experience in SQA for embedded software and firmware across one or more wireless protocols (Wi-Fi/BT/BLE/15.4) and coexistence of the protocols. Work closely with Software Development Teams, Program Managers, and Applications Engineers located across different GEOs and understand the key deliverables. Proficiency in Python and experience with working on embedded systems and embedded C applications. We are looking for creative, flexible, pragmatic, and skilled individuals with superb communication skills and a love of problem solving in a fast-paced team environment. How The SQA Team Works The Silicon Labs SQA team is a tight group of software professionals, with a broad understanding of Continuous Integration testing initiatives in wireless networks and a passion for innovation, quality, and providing business value through technology. We care about the business we support and take pride in the technology services we deliver and go the extra mile to “Do the Right Thing” for Silicon Labs and its customers. Members of our team appreciate that we are greater than the sum of our parts. The IoT SQA Team's Responsibilities The IOT Software Quality Assurance (SQA) Team at Silicon Labs which is spread across several different geographical locations, focuses on improving the overall quality of the Silicon Labs SiSDK Product. The SiSDK products contain all the wireless (Wi-Fi, Bluetooth Low Energy (BLE), Bluetooth Mesh, Zigbee, OpenThread, Wi-Sun, Z-Wave, and proprietary protocols) and 32 bit micro-controller (MCU) software required to build end products for the Internet of Things (IoT) Market. Silicon Lab’s SQA Team works closely with the Software (SW) Development teams to ensure a deep understanding of the product, features and system functionality. Silicon Lab’s SQA Team utilize an internal test framework to automate all tests for repeatability and stability along with providing detailed test reports on each build of the product to provide our customers with quality assurance. The SQA team has decades of experience in providing high quality embedded SW products to our customers which include the largest names in the industry. Technologies we use: Java, Junit, Python, Jenkins, Docker, Cloud Based Computing, SQL Database, Windows, Linux, Shell, Bash, GIT Experience Required 9+ years of overall experience in wireless field in one or more wireless protocols (Wi-Fi/BT/BLE/15.4) 3+ years’ experience testing Coexistence between two or more protocols is preferred. Proficiency in resource management and tracking tools like Jira, confluence etc. Possess a strong sense of responsibility and an ability to work independently under minimal supervision Communicate well and work well in a cross-functional team environment Experience working with cross GEO team members, attending meetings, and identifying actions items between teams for successful delivery of projects. We Consider The Following Experience As a Plus Experience with continuous integration and continuous deployment (CI/CD). Experience testing or developing embedded SW products Knowledge of version control systems, such as git. Knowledge in programming languages such as C++ or Java, as well as scripting languages such as Perl, Python, or Tcl Expect Data communications and networking. Education And/or Experience Minimum of Bachelors of Science in Electrical Engineering or Computer Science from four-year college or university preferred; or equivalent combination of education and experience. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

L&T Technology is looking to hire for Design Verification Engineers. Job Location : Bangalore Detailed JD is below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVNJob Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Show more Show less

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVN Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074279 Show more Show less

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance Job Description The position involves designing, developing and deploying UVM/C based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I3C, PWM. Responsibilities: Develop and track execution of chip level test planning to meet product requirements and established quality standards Lead a team to complete the pre-silicon verification of an SoC Execute and maintain chip level verification regressions. Triage and debug failing tests. Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification. Perform gate level verification across corners. Provide appropriate activity files for power analysis. Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure. Experience Level: 10-15 years in Industry Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage. Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Very strong Analytical debugging skills Knowledge on C Based Testcases. Knowledge of SoC,Memory and Cache Architectures Knowledge on Low power designs and architectures Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

Who We Are We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies, and improve lives. www.silabs.com About the team The IoT Digital Design team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide best in class technology solutions through innovation in custom RISC-V Cores and AI/ML components. What we’re looking for: Silicon Labs is seeking a Lead Engineer for the Emulation and Prototyping Platform (EPP) team. The position requires a thorough FPGA development and deployment background with focus on automation to efficiently deliver an emulation platform. Technical leadership and Mentorship experience preferred. Skills you’ll need: Deliver emulation platforms to internal groups to enable pre-silicon verification, validation, and software development. Provide hands-on technical leadership and training for staff. Schedule development, task assignment, and tracking to meet project milestones. Robust quality assurance metrics defined, documented, measured, and reported. Collaboration with internal teams and external vendors to define needs and set expectations. Identify and execute strategic initiatives to advance team delivery. Coordinate emulation and prototyping activities with a global engineering team. Communicates technical information and schedules to senior members of the management team. Functional Role: Worked with industry standard emulation and simulation tools. Ability to understand HDL language and understand HW/SW Codesign. Understand CDC, STA and other timing considerations in the context of FPGA. Advanced knowledge of clocking, memory and other FPGA needs. Experience with Lab equipment like Digital Signal Analyzer and Signal Generator. Knowledge of scripting languages like TCL, perl and python. Previous experience with Linux based version control environment (GIT, Perforce, Methodics). Worked with SystemVerilog and UVM testbench. Job Automation skills like Jenkins and Docker. Embedded C programming. PCB knowledge for schematic, layout, signal integrity consideration etc. Chip integration and bring-up experience. SW, Tooling and DevOps knowledge. Education and/or Experience: 6-8 years in Industry Bachelor or master’s degree in electrical and/or Computer Engineering Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability. Show more Show less

Responsibilities: * Ensure compliance with industry standards and customer requirements. * Design DFT solutions using ATPG, MBIST, Scan Insertion, JTAG tools.

Develop RTL (Verilog/SV) per microarchitecture specs, integrate IPs, perform lint/CDC, support synthesis. Strong in digital design, AMBA (AXI/AHB), low-power (UPF), TCL/Python. Tools: DC, Genus, SpyGlass. Collaborate on debug & reviews.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled & experienced engineer with SDC/RDC/CDC skills to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities: As part of the Design Enablement team of the organization, you need to collaborate with design and verification teams to implement robust CDC/RDC solutions into organization standard flows You will work with EDA Vendors to proactively review latest tools and flows offerings in this domain & evaluate latest offerings and benchmark with organization used tools, flows, and methodologies You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain 10+ Years of Experience Expertise in RTL Level checks understanding Expertise in CDC verification tools like Mentor Graphics Questa CDC and Synopsys SpyGlass CDC Expertise in utilizing tools like Synopsys Prime Time, Cadence Tempus, and Mentor Graphics for timing analysis Expertise in utilizing RDC verification tools and methodologies to identify and resolve reset-related issues. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can – do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments JD:- Asic RTL Design: Digital Design Knowledge RTL coding – System Verilog/Verilog/VHDL SoC integration experience is preferred CDC, Linting knowledge Synthesis, STA, DFT, Layout reviews experience Skills Rtl Coding,SOC integration,CDC Show more Show less