Job Description In this position, you will be responsible for managing and working on all aspects of SOC Physical design flow, STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to:Design and Architecture understanding. Interaction with FE/DFT/Verification teams. Synthesis, floor planning, placement, routing, clocking, Constraints development. Understanding on synchronous and asynchronous paths, Clock domain crossing issues, deciding timing signoff modes and corners, Design margins. Hierarchical timing including IO budgeting for partitions. Drive the designs to timing and physical design closure. Performs physical design implementation of SOC from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, and power and noise analysis. Qualifications Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6-12 years' of experience. Key skills: In-depth knowledge and hands-on experience in all aspects of physical design flow in SOC such as synthesis, place, clock tree synthesis, route and signoff. Good understanding and exposure of overall Timing closure cycle in SoC. Experience in deep submicron process technology nodes is strongly preferred Solid understanding industry standard tools for synthesis, place and route(Fusion Compiler) and timing flows. Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT). Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 1-3 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Bachelors / Masters degree in electrical or electronics engineering with 1-3 yrs of experience is preferred

Position: Synthesis + STA Engineer Experience: 5+ yrs Qualification: B.Tech / B.E or M.Tech / M.E. Job Location: Bangalore Job Type: Permanent & Day Shift Responsibilities: Experience in handling complex data path oriented multi-million gate synthesis. Working Knowledge on Physical synthesis using tools like Genus, Fusion Compiler • Experience in developing constraints for multi-clock domains hierarchical/flat timing analysis • Good working knowledge in multi-power domain synthesis and structural power checks using CLP. • Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts. • Good working knowledge in Pre-lyt STA and analyzing timing reports and generating timing ECOs • Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion. • Exposure in TCL scripting for usage in Synthesis/STA • Knowledge on Hierarchical STA with Hyperscale is a plus • Good team player. Need to interact with the stakeholders proactively • Ability to debug and solve issues independently Minimum Qualifications • Bachelors degree in engineering, Electronics, or related field. • 5 to 8 years Hardware Engineering experience or related work experience. We are looking out for candidates who can join 15 to 30 days notice max. Please share your updated profile to: ravindra.m@creenosolutions.com or you may reach out 83040937197

Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bit cells, SRAMs, Register Files). Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding. Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom autorouters and custom placers to efficiently construct layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Develops and drives new and innovative layout methods to improve productivity and quality. Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design. Qualifications A BS/BE/BTech in Electronics Engineering with exposure to designing and optimizing VLSI layout at the cell and/or block level is required. Additional Desired Qualifications Good knowledge of VLSI process and device physics Exposure to physical verification tools, including DRC, LVS, ERC, density, and DFM checks. Unix and shell scripting exposure Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool Knowledge of scripting languages TCL, Perl, Skill, Python for design automation is a plus

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Additional Job DescriptionJob description: As an IR/PDN Design automation engineer responsibilities would involve deploying new features/methodologies related to IR and IR-STA domain. Scope of the work would cover IR flow/methodology development, productivity improvement, QCOM Flow development and Support for IR Closure IR/PDN Closure (SOC and Block Level) involves a multi domain analysis -Physical, Electrical and Timing and this complex closure on lower technologies can pose challenging problems that would require a grasp across multiple domains Key requirements: Thorough knowledge of the ASIC design cycle. Good understanding of IR/PDN Methodology. Expertise in IR tools (RHSC, Voltus) . Good Understanding of basic STA concepts. Good at scripting languages (Python, TCL, Perl). Exposure to PNR and Extraction domain. Qualities like team player, fast learner and highly motivated Qualification: BE/BTech + 2 years of experience, or ME/MTech + 1 years of experienceYou may e-mail or call Qualcomm's toll-free number found .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements Required:Bachelor's, Electrical Engineering or equivalent experiencePreferred:Master's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need: BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience: MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areas:Microprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Wipro Limited (NYSE:WIT, BSE:507685, NSE:WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSE:WIT, BSE:507685, NSE:WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role : Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

About The Role : The candidate will be expected to perform Development and support for DRC/LVS/PEX/PERC runset(ruledeck) generation on Intel's process. Development/support of ICV/Calibre/Pegasus/PVS runset (rule deck) for DRC/LVS/PEX/PERCConduct the L0QA of the codes. Bring in run time efficiency, automation and solve customer issues on rusets. Develop and maintain DRC/LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Qualifications Candidate needs to have:- B.tech or M.tech with 8+ years of experience in DRC/LVS/PEX/PERC runset development/QA on ICV/Calibre/Pegasus tools/flow.- Strong CMOS concepts- Strong debugging and scripting skills- Strong team working and leadership skills.- Layout tools:Virtuoso, CalibreDRV, IC Work Bench- Runset Development:Calibre, PVS, ICV, Pegasus- Scripting :Unix, Perl, Python or TCL Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

About The Role : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications Bachelor Degree in Electrical and Electronics Engineering or Master's Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Working Model This role will require an on-site presence. *

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification.Influence tools, flows, and overall design methodology in design construction, signoff, and optimization.Work closely with architecture/RTL/DFT/DV/Package development teams.Be a technology expert in the area of Physical Design with in the team and business Unit. Minimum Qualifications 10 to 15 years of experience in Physical Design.Proven experience in implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification.Technically lead a team of PD engineers on the Physical Design activities of complex SoCs. Strong understanding of constraints generation, timing optimization, and timing closure and STA.Strong technical problem solving and debugging abilityExperience in EDA tools related to Place and route, Synthesis, Physical Verification , STA etc.Proficient understanding of CTS and different clock building techniquesExperience with multi-clock, multi-power-domain design, UPF etcExperience in IP integration (memories, IO’s, embedded processors, hard macros, Analog IP)Knowledge of Microelectronics conceptsScripting skills in Python, Tcl, C etcAbility to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvementsGreat communication and teamwork skills For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

About The Role : Require Extraction expert with 8+ years' experience. The candidate will be expected to perform Development/support for extraction solutions for gate level and/or transistor level to build high quality PDK on STARRC/QRC. Development/support of ICV/Calibre/Pegasus runset (rule deck) for parasitic extraction, correlate parasitic coming from different extraction flows, assume ownership of entire LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Candidate is expected to have great stake holder management and leadership skill. Qualifications B.tech or M.tech with 8+ years of experience in runset development/QA on ICV/Calibre/Pegasus tools/flow. Expertise in Parasitic extraction tools like StarRC, QRC , xACT. Strong debugging and scripting skills. Strong team working and leadership skills. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Job Title PLM Enovia Developer Responsibilities A day in the life of an Infoscion As part of the Infosys consulting team, your primary role would be to get to the heart of customer issues, diagnose problem areas, design innovative solutions and facilitate deployment resulting in client delight. You will develop a proposal by owning parts of the proposal document and by giving inputs in solution design based on areas of expertise. You will plan the activities of configuration, configure the product as per the design, conduct conference room pilots and will assist in resolving any queries related to requirements and solution design You will conduct solution/product demonstrations, POC/Proof of Technology workshops and prepare effort estimates which suit the customer budgetary requirements and are in line with organization’s financial guidelines Actively lead small projects and contribute to unit-level and organizational initiatives with an objective of providing high quality value adding solutions to customers. If you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you! Technical and Professional Requirements: Primary skills:PLM,PLM->Enovia Desirables:IOT Preferred Skills: Technology->PDM / PLM->Enovia Generic Skills: Technology->Enterprise Package Processes->PLM Upgrade Process->PLM Additional Responsibilities: Ability to develop value-creating strategies and models that enable clients to innovate, drive growth and increase their business profitability Good knowledge on software configuration management systems Awareness of latest technologies and Industry trends Logical thinking and problem solving skills along with an ability to collaborate Understanding of the financial processes for various types of projects and the various pricing models available Ability to assess the current processes, identify improvement areas and suggest the technology solutions One or two industry domain knowledge Client Interfacing skills Educational Requirements Master Of Comp. Applications,Master Of Engineering,Master Of Science,Master Of Technology,Bachelor Of Comp. Applications,Bachelor Of Science,Bachelor of Engineering,Bachelor Of Technology Service Line Engineering Services * Location of posting is subject to business requirements

About The Role : About The Role ::In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII.You will be part of ACE Group, in the P-Core design team driving Intel's latest CPU's in the latest process technology.Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design. Static timing analysis. Power Optimization. Design Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with atleast 10 or more years of experience in related field or a Bachelors Degree with at least 12 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications:- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role : Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with 2-3+ years experienceExperience Skills: SoC Place and Route Physical design Layout convergence experience. Basic programming skills UNIX shell script Tcl Perl Python Additional qualifications include Proficiency in multiple levels of layout design which includes partitions, subsystems Proficiency in floor planning activities which include Par unit level assembly routing and integration of partition, section, custom blocks in to the FC floorplan Ability to comprehend issues of RC delay electromigration self heating and cross capacitance Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. Technical Expertise in Static Timing Analysis is preferred. Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills

Responsibilities Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC.. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) Good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PERL ,SKILL and/or TCL

Responsibilities We are seeking highly motivated individuals with a BS, MS, Btech or Mtech degree in Electronics engineering to be part of the EDA team. Join a great team of engineering professionals who are involved in development, validation & release of IBM CAD tools & methodologies used in designing IBM P & Z microprocessor systems along with system ASICS. In this role, you are expected to enable different flavours of the backend design( RTL-GDS ) flows and assess the quality of tools. Develop automation scripts to aid tool in data analysis/visualization. You are required to have excellent debugging skills and have good understanding of RTL-GDS implementation flow for 7nm and below technologies. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMer? Come THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Good knowledge and understanding of PD optimization flow and signoff checks. Excellent scripting skills - TCL/Python/Shell Proven problem solving skills and the ability to work in a team environment are a must Good communication skills & the skill to work with teams across geographies. Ability to continuously improvise and innovate to resolve challenges efficiently. 2+ years of experience in software/methodology development or support in physical design domain. Preferred technical and professional experience Cadence, Synopsys, VLSI knowledge, VHDL/Verilog, Machine Learning/AI

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree in electrical/Electronic Engineering. To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm , 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification :DRC, LVS, Calibre Secondary Skills IO layout

About The Role : ou will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks. Your responsibilities will include but not limited to: 1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).3. Expertise in Static timing analysis concepts.4. Close work with Layout and Floor planning teams.5. Back end design implementation of new features.6. Expertise in Memory post silicon analysis. 7. Good understanding of statistical variation. 8. Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores. Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred. Preferred Qualifications: 1. Digital Design Experience, with High Speed, Low Power.2. Familiarity with Verilog/VHDL.3. Tcl, Perl, Python scripting. 4. Good understanding of spice simulations and analysis 5.Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Emulation Enginner (Zebu, Model build, Transactors, Palladium,HAPS, Model Build, Protium Work Location - Bengaluru, Hyderabad, Pune, Noida, Kochi 1) A good understanding of architectural aspects and RTL code at IP/Sub-system/SoC level 2) A good understanding of verification methodologies including SV-UVM/C based environment, transactors etc 3) Experience in building emulation models from scratch 4) Knowledge of Arm CPU cores, protocols including PCIe, USB, Ethernet, AMBA, UART/SPI/I2C, DDR, flash memories and their usage in SoC environments is necessary 5) Emulation experience on ZeBu /Veloce/Palladium, including compilation, test execution, debug, and performance. 6) Strong scripting skills including UNIX shell scripting, Perl, TCL etc 7) Support various emulation users 8) Must have worked in end-to-end Emulation of atleast 1-2 SoC programs in Sub-system and chip level

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 6-8 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python ,SKILL and/or TCL Environment: Professional knowledge related to incumbent's function/business unit and its processes.Communication/Negotiation: Advise other professionals. Effectively utilize group dynamics. Negotiate to define approaches and goals.Problem Solving: Recognize complex problems related to functional objectives. Analyze situations and implement solutions, or develop new system elements, procedures or processes. Creativity and judgment applied to developmental work on different projects within the business environment. Contribution/Leadership:Provides ongoing technical /operational guidance to lead professional work teams, conducts special projects, or manages department(s) (national or international). Understand department/ functional mission and vision. Defines and decides objectives within specified business concept or project and may have responsibility for tools and assigned resources. Utilizes expertise to directly influence people outside department or function. Sometimes no precedent exists.Impact on Business/Scope:Accountable for department results and for activities and/or projects involving multi-functional teams. Regularly participates in overall functional program planning. Activities are subject to business measurements, impact customer satisfaction, and impact project costs or expenses.

Finite Element Analysis - Simulation - Static & Dynamic. Using tools like Hyperworks & Abaqus tool. Worked in global set up Exposure to product dev process Structural (Linear/Nonlinear static & Vibration) Simulation. Thermal & Fatigue Stimulation. Required Candidate profile Background on Research & dev projects & conduct comprehensive literature surveys. Digital Twin-have a basic understanding or exposure. Exposure to Multi Body Dynamics. Knowledge of Python or TCL / TK