1597 Tcl Jobs - Page 36

Experience: 5+Years Job Location : Hyderabad The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable). · Knowledge of invoking the MATLAB DPI checker (or any foreign language) in the UVM

Job Description: We are seeking a skilled and motivated DFT Engineer with at least 2 to 10 years of industry experience in Design for Test in the VLSI domain. As part of our SoC Design team, you will play a key role in implementing and validating DFT architecture to ensure high test coverage, low DPPM, and efficient silicon debug capabilities. Key Responsibilities: Develop and implement DFT architecture for complex ASICs and SoCs. Integrate and verify DFT features such as: Scan insertion and ATPG Memory BIST (MBIST) Logic BIST (LBIST) JTAG/IEEE 1149.1 (Boundary Scan) Test compression techniques (e.g., Tessent, Synopsys DFTMAX) Work closely with RTL, synthesis, and backend teams for DFT implementation and sign-off. Run and debug simulations for scan and BIST logic. Work with Automatic Test Equipment (ATE) teams to bring up and validate silicon. Support post-silicon debug and yield improvement efforts. Collaborate with cross-functional teams including verification, physical design, and validation. Required Skills: 2+ years of hands-on experience in DFT implementation and test methodology. Strong knowledge of scan insertion, ATPG, and fault grading. Experience with DFT tools such as: Synopsys (DFTMAX, TetraMAX) Mentor Tessent Cadence Modus Proficiency in Verilog/VHDL, TCL, and shell scripting. Understanding of digital design and SoC architecture. Familiarity with STA and timing constraints related to DFT.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes ENOVIA V5 Good to have skills : Dassault Systemes 3DEXPERIENCE ENOVIA CustomizationMinimum 5 year(s) of experience is required Educational Qualification : Minimum 15 years of regular Education preferably BTECH or BE Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team members. You will also engage in problem-solving activities, ensuring that the applications are aligned with business needs and technical specifications. Your role will require effective communication and coordination with stakeholders to facilitate project success and drive innovation within the team. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Facilitate knowledge sharing and mentoring among team members.- Monitor project progress and ensure adherence to timelines and quality standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Dassault Systemes ENOVIA V5.- Good To Have Skills: Experience with Dassault Systemes 3DEXPERIENCE ENOVIA Customization.- Strong understanding of application design and development processes.- Experience with configuration management and version control systems.- Ability to troubleshoot and resolve technical issues effectively. Additional Information:- The candidate should have minimum 5 years of experience in Dassault Systemes ENOVIA V5.- This position is based in Chennai.- A Minimum 15 years of regular Education preferably BTECH or BE is required. Qualification Minimum 15 years of regular Education preferably BTECH or BE

Skill required: Marketing Operations - Operations Management Designation: PPSM Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years About Accenture Combining unmatched experience and specialized skills across more than 40 industries, we offer Strategy and Consulting, Technology and Operations services, and Accenture Song all powered by the worlds largest network of Advanced Technology and Intelligent Operations centers. Our 699,000 people deliver on the promise of technology and human ingenuity every day, serving clients in more than 120 countries. Visit us at www.accenture.com What would you do This role ensures smooth and Client compliant running of P2P processes across Global Marketing and GAM teams. What are we looking for Education:High-school diploma or equivalentExperience Managing business and financial data, working with business systems and processes Managing time, prioritisation of workload, and stakeholders Significant experience in P2P process and SAP systems Ability to work both in a team and independently Previous experience in a global functional and geographic matrix organisation.Skills & CompetenciesStrong data management skillsHighly proficient with MS Excel (pivot tables, lookups, formatting, calculations)Proficiency in use of business systems SAP, PRL, RRV, FIORI, ARAVO (CCD)Familiarity with Finance core processes accruals, GRIRSelf-starting; can prioritise own workload and manage stakeholders expectationsMeticulous attention to detail, including when delivering under time pressureHolds others to account for following Client processesProject & Relationship Management (Skilful)Market Understanding (Skilful)Performance Monitoring (Skilful)Continuous Improvement (awareness) Roles and Responsibilities: To support Global Marketing & GAM in P2P ProcessesThe raising and receipting POsEnsuring POs are raised against correct cost centres, IO codes & GL codes.Tracking of POs and maintaining reports to provide info on all POs raised, working with Finance team and giving visibility to marketing teams to support budget management.Resolving issues with POs as highlighted by the lubes query tracker, working with vendors, procurement and budget holders to ensure issues that may prevent payment of invoices are resolved within payment terms.Problem solving role involves seeking solutions outside of own remit and liaising with numerous other teams (Finance, Procurement, GBS)Continuous improvement in reporting to ensure it meets the needs of budget holders and increases visibility and tracking of ASP spendResponsible for managing issues related to mismatches between goods receipt and invoice receipt as detailed on the GRIR reports.Responsible for setting up new vendors and amending vendor details in the SAP system, liaising with budget holder, vendor, procurement, CCD team to ensure all relevant documents and approvals correctManaging payment schedules, monthly fees and subscriptions and arranging upfront and advance paymentsProvide ongoing training and support to the budget holders on the correct ways of working to ensure compliance to Company Policy.Responsible for keeping the P2P procedures up to date and published on the GlobalMarketing SharePoint site and maintaining the P2P SharePoint site and other digital interfaces, as assigned Responsible for reporting breaches of company policy Qualification Any Graduation

Project Role : Industry Subject Matter Advisor Project Role Description : Work closely with client project teams to provide expertise (functional, technical, industry, tools/methods) to ensure successful solution design and delivery. Must have skills : SAP for Utilities Cust Financial Mgt FICA Good to have skills : SAP for Utilities BillingMinimum 7.5 year(s) of experience is required Educational Qualification : BE BTech Summary :As an Industry Subject Matter Advisor, you will work closely with client project teams to provide expertise (functional, technical, industry, tools/methods) to ensure successful solution design and delivery. Your typical day will involve collaborating with the client project teams, offering your expertise in SAP for Utilities Cust Financial Mgt FICA, and contributing to the design and delivery of solutions. Roles & Responsibilities:- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Contribute to the successful solution design and delivery- Offer expertise in SAP for Utilities Cust Financial Mgt FICA- Provide functional and technical guidance to client project teams Professional & Technical Skills: - Must To Have Skills: Proficiency in SAP for Utilities Cust Financial Mgt FICA- Good To Have Skills: Experience with SAP for Utilities Billing- Strong understanding of the utilities industry and its financial management processes- Experience in solution design and delivery for utilities customer financial management- Knowledge of industry-specific tools and methods for utilities solution design- Ability to provide functional and technical guidance in SAP for Utilities Cust Financial Mgt FICA Additional Information:- The candidate should have a minimum of 7.5 years of experience in SAP for Utilities Cust Financial Mgt FICA- This position is based at our Pune office- A BE BTech degree is required Qualification BE BTech

Responsibility To support in design activities as per project requirement and deliver with quality and respect timelines. Adhere and maintain process related and applicable documents Coordinate with internal team and customer for project related queries and clarifications Maintains process related and applicable documents Required Skills: Under minimal guidance able to concepts and detail design of mounting definitions for mechanical equipment /subsystems. Knowledge on Sheet metal component design, material and processes. Knowledge on welded joints, symbols and implementation. Ability to compute and represent mass on assemblies, aggregates and installations Ability to understand Functional Dimensioning requirements. Design for manufacturability, serviceability. Selection of fasteners and joint design. Able to perform basic calculation. Good knowledge of drawing rules and GD&T using relevant standards. Hands-on experience in 3D, 2D and 3DFTA for modeling and detailing of parts, assemblies and installations using CATIA V5 and PLM tools like Enovia. Total Experience: 4 to 8 years

Responsibility To support in design activities as per project requirement and deliver with quality and respect timelines. Adhere and maintain process related and applicable documents Coordinate with internal team and customer for project related queries and clarifications Maintains process related and applicable documents Required Skills: Under minimal guidance able to concepts and detail design of mounting definitions for mechanical equipment /subsystems. Knowledge on Sheet metal component design, material and processes. Knowledge on welded joints, symbols and implementation. Ability to compute and represent mass on assemblies, aggregates and installations Ability to understand Functional Dimensioning requirements. Design for manufacturability, serviceability. Selection of fasteners and joint design. Able to perform basic calculation. Good knowledge of drawing rules and GD&T using relevant standards. Hands-on experience in 3D, 2D and 3DFTA for modeling and detailing of parts, assemblies and installations using CATIA V5 and PLM tools like Enovia. Total Experience: 4 to 8years

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Title: Software Engineer (JAVA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: As part of the global manufacturing systems engineering team, you are responsible for developing and maintaining software automation solutions in highly complex semiconductor factories. You will interface closely with the engineers from the manufacturing modules in Dresden/Singapore as well as with the partners of other international locations. After initial training, the successful applicant will have the opportunity to grow responsibility for projects and processes of strategic importance within the GLOBALFOUNDRIES Manufacturing cluster. This position is open to experienced engineers as well as to entry level candidates, including University or College Masters. Your Job : Build and Support various full-stack applications running in our Manufacturing locations. Responsibility for analysis, design, and implementation of automation software solutions in a highly automated manufacturing environment. Maintenance and continuous improvement of existing factory automation software solutions. Provide Second Level support for the applications owned by the team. Continuously learn leading technologies and trends in the software industry. Mentor other team-members on areas of competency. Required Qualifications : BS with 2-4 years of experience or MS with 1-3 years of experience. Programming skills in a high-level language (Java, C #). Basic knowledge of a scripting language (TCL, Perl, Python). Basic knowledge of SQL and relational databases. Fluent in speaking and writing in English and work with pleasure in international teams. Analytical thinking, high affinity for working in complex systems. Enthusiasm for the combination of software development with factory automation Preferred Qualifications: Proficient in Java 8+ or latest version programming as per the user story and hands-on with the technical skills necessary for delivering the module. Java/J2EE, REST, SOAP, Spring Boot, Spring JPA, Hibernate/JPA Knowledge on front end framework like ReactJS, typescript, Angular Aware of different techniques and tools available within DevOps. Contribute to the devOps team for implementation and execution. Maintaining source code & documentation as per defined Configuration Management process [E.g.: Bitbucket, GitHub]. Good to have knowledge of Linux commands. Experience with Manufacturing Domain and ERP solutions will be helpful. Good knowledge of the application server configuration. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued, and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation, and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Welcome! Our Growth is Creating Great Opportunities! Our team is expanding, and we want to hire the most talented people we can. Continued success depends on it! Once you've had a chance to explore our current open positions, apply to the ones you feel suit you best and keep track of both your progress in the selection process, and new postings that might interest you! Thanks for your interest in working on our team! Duties and Responsibilities: Performance of E2E System level test and test automation of GFAST solution (DPU, PMAA and MCP Plugin) includes GFAST solution testing, test automation using Python & Robot framework, CI Pipeline development, administration and Maintenance, Jenkins job configuration and control, Pipeline execution, failure analysis, fix the failures, re-run the tests and report the issues. Test automation development for GFAST products of new feature NFR, Provide support to the customer deployment and field/lab trials etc. Basic Qualifications: Bachelor / master’s degree in computer science, Computer Engineering, Software Engineering, Computer Information Science, or B Tech/BE/MTECH/MS in ECE or in CSE equivalent education required. At least 5-8 years of active experience. Programming skills in Python, Robot framework, Selenium, Shell scripting Experience on Layer2 & Layer3 protocols like VLAN, DHCP, PPPoE, LACP, IGMP. Should be familiar with device configuration protocols of CLI, NETCONF, SNMP. Experience in telecom technologies like DSL, G.fast, GPON, XGSPON, technologies is highly recommended Knowledge on software Test cycle, test plan / test case creation and participate in development of test strategies Understanding of End-to-End test setup topology with excellent debugging skill Ability to perform System level Functional, Non-functional tests and run regression testing on new software/hardware Develop and execute tests to validate customer use cases, ability to Reproduce field issues and validate their resolution Exposure to CI/CD pipeline implementation and maintenance using Jenkins, Groovy scripting Bug reporting/tracking and providing logs Preferred Qualifications: Have worked on testing of ONT/OLT/GFAST products Have experience in testing Interop between various products Hands on experience with different Traffic generators like Spirent , ixia, Abacus, Shenick etc. Automation /scripting knowledge using Tcl/Python/and Robot framework Use traffic generators to create real-world traffic streams for video, data, and voice related testing Success Criteria: Good self-organization “Self-starter, get things done” mindset. Desire and ability to learn. Compensation & benefits: Competitive salary package 18 to 23 annual leave entitlement Group medical insurance with coverage for family members. International exposure Strong team-oriented and friendly work culture Financial assistance to further education Access to Adtran University Access to various staff activities and events

Role: Senior Design Verification Engineer (PCIe) Role: Bangalore Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, score boarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in System Verilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, Sim Vision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers Job Types: Full-time, Permanent Pay: ₹4,000,000.00 - ₹5,000,000.00 per year Benefits: Cell phone reimbursement Health insurance Paid time off Provident Fund Schedule: Day shift Work Location: In person

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor’s or Master’s in Electrical/Electronics Engineering, or related field with 2–5 years of relevant experience . Proven expertise in physical design CAD flows , including floorplanning, place-and-route , timing, and power analysis. Strong scripting skills in Tcl and Python ; automation experience is a must. Hands-on experience with advanced technology nodes ( 5nm or below ). Proficiency in industry-standard tools like Cadence Innovus . Solid understanding of digital design, timing closure, and physical verification. Experience collaborating with cross-functional teams (RTL, PD, CAD, EDA vendors). Ability to develop and support high-performance CAD tools and methodologies. Strong analytical skills to debug and optimize tools/flows. Excellent communication skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Physical Deisgn Lea LocationBangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experienceon Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: VLSI Physical Place and Route. Experience5-8 Years.

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We have created the popular ESP8266 and ESP32 series of chips, modules and development boards. By leveraging wireless computing, we provide green, versatile and cost-effective chipsets. We have always been committed to offering IoT solutions that are secure, robust and power-efficient. By open-sourcing our technology, we aim to enable developers to use Espressif’s technology globally and build smart connected devices. In July 2019, Espressif made its Initial Public Offering on the Sci-Tech Innovation Board (STAR) of the Shanghai Stock Exchange (SSE). Espressif has opened a Technology Center in Pune (Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers. About Role Job Responsibilities Digital IP design Perform Lint/CDC/LEC/DFT/Low-Power analysis Module level synthesis and timing constraints Must have worked on ARM/RISC-V CPU based designs Familiarity with FPGA/Silicon validation using C based tests and usage of standard debugging tools Qualifications M.Tech/B. Tech in the field of VLSI/Electronics engineering with 4 to 8 years of experience. Proficiency in System Verilog for RTL logic design and verification. Strong understanding of CPU pipeline and computer architecture is a must. EDA tool knowledge of Design Compiler, PrimeTime is preferred. Automation skills in PERL and/or TCL and/or Shell* is an added plus. Team player, with good problem solving and communication skills. What to expect from our interview process The first step is to email your resume or apply to the relevant open position, along with a sample of something you have worked on such as a public GitHub repo or side project etc. Next, post shortlisting your profile recruiter will get in touch with you via a mechanism that works for you e.g. via email, phone. This will be a short chat to learn more about your background and interests, to share more about the job and Espressif, and to answer any initial questions you have. Successful candidates will then be invited for 2 to 3 rounds of technical interview as per previous round feedback. Finally, Successful candidates will have interview with HR. What you offer us Ability to provide technical solutions, support that fosters collaboration and innovation. Ability to balance a variety of technical needs and priorities according to Espressif’s growing needs. What we offer An open minded, collaborative culture of enthusiastic technologist. Competitive salary. 100% company paid medical/dental/vision/life coverage. Frequent trainings by experienced colleagues and chances to take international trips, attend exhibitions, technical meetups and seminars.

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks. Familiarity with DRC, LVS, and other physical verification processes. Responsibilities Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues. Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance. Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency. Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise. Experience: 4+ Years Job Location: Bangalore

ASIC DFx - MTS Silicon Design Engineer New Dehli, India Engineering 66377 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with formal model checking for ASICs and FPGAs, SystemVerilog and SystemVerilog Assertions. Experience with formal verification EDA tools. Experience with model checking frameworks such as Murphi or TLA+. Preferred qualifications: Master's or PhD degree in Computer Science, Electrical Engineering, or a related field. Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, 360-DV. Experience with a scripting language like Perl, Tcl or Python. Experience with propositional logic, theorem proving and tools such as Z3. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Partner with hardware architects for formal specifications and verification of system-level properties. Develop highly abstract models of various designs and prove architectural correctness within a model and consistency across models. Plan formal verification strategy, create the properties and constraints for complex digital design blocks. Translate system-level formal specifications into precise constraints for individual logical blocks. Architect and implement reusable formal verification components. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Greetings from TATA Consultancy Services Job Openings at TCS Skill :NETWORK ADMIN(Architect) Exp range :15+ Years (L3/L4) Role : Permanent Role Job location :Chennai/Hyderabad/bangalore Current location : Anywhere In India Interview date :27TH JUN 25(Friday) b/w 11:30 AM to 1:00 PM IST/ 30 MINS Interview mode : MS Teams Pls find the Job Description below. About the Role The Senior Network Engineer’s primary role is to support and manage customer’s 24x7 Network, primarily focusing on our European locations but may also be require supporting our US and ASIAPAC locations. The role requires a solutions specialist of Fintech grade network management talent, versed in Next Gen Firewalls, Switches, Routers, Load Balancers, Server Administration, NAC’s, Circuit Administration, Wireless AP’s and End User System Components. The Network Engineer will work closely with our NOC, SYS Ops, Database and Helpdesk teams to prepare, configure, deploy, support and troubleshoot real-time platform systems serving operational services and online transactional processing in direct support of Customer’s global portfolio and financial objectives. What you will do Designing, implementing, maintaining, and supporting local and remote portions of the PCI-DSS enterprise financial network. Deploy InfoSec-approved DC architecture based on existing best of breed design and emerging trends. Management of Campus/Partner connectivity via LL, VPN (IPSEC and SSL) & SDWAN SSL/TLS certificate management. Application Delivery management via DEV/QA/UAT/Prod support. Triage support for all LAN/WAN/Cloud related operations and infrastructure. Manage circuit provisioning, activations, and troubleshooting. Conducting regular security assessments of the enterprise IT environment. Participating in design and strategy meetings for assigned IT projects for the enterprise. Evaluating existing communications systems, identifying deficiencies and making network performance recommendations. Installing and configuring Physical Servers, Host VM’s and Data/Voice Communications equipment as needed. Responsible for performing off-hours maintenance as required. Who you are Fast paced and holds a high level of responsibility to ensure team objectives, issues and business concerns are dealt with in a timely manner. Ability to work with geographically disperse external/internal cohorts and outside financial partners while assisting AP based directives. Knows how to respond to escalation requests appropriately, efficiently, and effectively. Rotating On-Call support and resource alignment of time. Light Travel occasionally required. Required Skills/Experience Demonstrable experience in LAN/WAN, MPLS, QOS, multicast and core networking discipline, including advanced routing protocols, BGP, OSPF and IP converged networks Proficient OSI layer 1-7 troubleshooting. Ability to analyse, trace and understand a Packet along a transaction lifecycle end-to-end. Circuit, Vendor, Partner relationship and tracking experiencing. 1 - 3 years of experience in an enterprise level Network engineering role, which includes network administration experience with Cisco, Fortinet, F5, Checkpoint, Kubernetes/K8S, Mellanox, Azure and other quadrant-defined vendors. Working experience with next generation architectures: private/public/hybrid cloud, containers and hyper-converged infrastructure. Knowledge of network domain administration, platforms and principles, to include route/switch protocols, WAN/LAN, wireless networking, datacentre, high-availability design, Application Delivery Controller, Web Application Firewall, Domain Name Service and IP management, Cloud Platforms, Denial of Service Protection, Data Analytics and Network Monitoring. Desired Skills/Experience IPS, DDOS, 802.1X, NAC, ISE, AV implementation experience. ISO 8583, PCI-DSS, GDPR compliance and standardization. Scripting in TCL, Python a, knowledge of VMware ESX, Whitebox Switching/Cumulus Linux, Wireshark/PCAP, ELK, Wazuh, FortiClient. F5 LTM, Fortinet FortiGate’s, FortiAP’s, Mellanox. Cisco MLS platform’s, Checkpoint/SPLAT familiarity. Qualifications Network+/KCA/CCNA/CCNP/NSE4/CISSP preferred. Bachelor’s degree or equivalent education and/or experience. Thanks & Regards Priyanka Talent Acquisition Group Tata Consultancy Services

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description Own and deliver on design verification of complex Intellectual Property (IP) or Subsystem or complete full chip (SoC) level features and mixed signal subsystems. Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC. Develop test methodologies, strategies, reviews and supervise execution of test plans. Develop verification environments involving directed, formal, constrained random stimulus and coverage driven verification; run and debug simulations to drive quality. Execute test plans for complex design areas or products by leveraging teams, as well as through individual contributions. Set targets for test coverage and strategy to achieve coverage. Ensure quality of test plan execution across broad areas. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Innovate to improve verification efficiency through methodologies, processes or tools. Provide technical leadership through coaching, mentorship, modeling and teamwork. Demonstrate ADI core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact and Diversity & Inclusion. Minimum Qualifications Bachelor’s or master’s degree, in Engineering (Electronic Engineering) or equivalent Excellent debugging and analytical skills. 10 – 12 years in ASIC design verification. Additional Qualifications & Experience: Verification Planning tools (ePlanner, vManager) Property Specification Language (PSL), SystemVerilog Assertions (SVA) Proficient with Cadence Suite (Virtuoso IUS) Scripting languages (Shell, TCL, PERL, Python) for bench automation Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog. Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer. Coding up in C tests on M3 Series Cortex based products. Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Soc Power Architecture - Power Artist/PTPX Hyderabad, India Engineering 66223 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Requirements: Experience: 5+ Years At least 5 years of experience in the networking domain (ethernet preferred). CCNA level of understanding is a baseline. CCNP is a plus. Dev-test experience (regression test monitoring experience will not suffice). Demonstrate hands-on test development for L2/L3 protocols. Exposure to basic C (may not have to write C code but should be able to understand functions/arguments/structures). Good scripting skills in TCL (exposure to python is OK but need to be willing to work in TCL). Analytical problem-solving skills should be able to come up with test scenarios. Should be willing to work with TCL infra and interact with simple C API call-based scripts. Qualification: Bachelor’s degree in computer science, Engineering, or a related field Job Category: Software Tester Job Location: Bangalore Job Country: India

Requirements: Experience: 4+ Years At least 4 years of relevant automation experience (networking sector) Proficiency with scripting (Python/TCL, shell) Ability to automate interactive sessions with devices (ssh/telnet/console) Ability to develop scripts/libraries to work with third party device comms libraries (e.g. ixia, spirent traffic generators) Develop reporting schemes (serverless database, web interfaces) Familiarity with Jenkins, git. Qualification: Bachelor’s degree in computer science, Engineering, or a related field Job Category: Software Tester Job Location: Bangalore Job Country: India

Company Description Mempage Technologies is dedicated to providing Product Engineering Services and building future technologies to simplify life. We specialize in R&D, MVP, product development, and technology services that empower and transform society, focusing on security and privacy through cutting-edge technologies such as AI, IoT, Edge, and Cloud computing. We develop AI-IoT-5G enabled products in areas like Smart Agriculture, Smart Grid, Healthcare, Logistics, and Gaming. Furthermore, we offer services in Application Development, Salesforce, Oracle, and UI/UX. Our global presence includes offices in India, Malaysia, and the USA, serving top clients such as Emaar, Radisys, AMD, and Qualcomm. Role Description This is a full-time, on-site role for a Post-Silicon Validation Engineer/Embedded Test Engineer at our Hyderabad office. The engineer will be responsible for validating and debugging embedded systems, conducting functional verification, and ensuring compliance with Good Manufacturing Practice (GMP). Daily tasks include RTL design, validation, and implementation of test strategies designed to identify and resolve system bugs and performance issues. Collaboration with cross-functional teams to enhance product development and ensure high-quality deliverables will be essential. 🧠 Experience: 3–6 Years 🕐 Notice Period: Immediate to 30 Days Preferred 🔧 Key Skills Required: • Strong programming skills in C/C++ • Familiarity with AMD tools – Vivado, Vitis • Experience in scripting using TCL/Python • Sound understanding of Embedded Systems • Knowledge of hardware: Processors, SoC, FPGA, Memory interfaces • Hands-on with communication protocols: SPI, I2C, USB • Excellent problem-solving and hardware debugging skills • Basic working knowledge of Linux 📩 Send your profiles to: akshita@mempagetech.com