1570 Tcl Jobs - Page 3

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

As a Senior Network Test Engineer in the SP Routing "Customer solution validation team within Cisco's Core Software Group, you will have the opportunity to work with some of the industry's finest talent pool and be part of a team where work is both fun and challenging. The team is responsible for all Software Development/Test functions across Service Provider Routing and Optical platforms, owning a large portfolio of high-density core/edge routing platforms that power global networks. Your impact will involve architecting, designing, developing, and testing some of the world's largest Service Provider Routers that are continuously evolving to support new customer business paradigms. You will play a crucial role in testing and automating Cisco's Next-Gen Routing platforms, building automation infrastructure, and programming for the IOS-XR family of routers. This position is ideal for engineers who are high-energy, motivated, thrive on technical challenges, and are eager to shape the future of networking technology. Key Responsibilities: - Testing and automating advanced networking protocols including L2, L3, MPLS, BGP, OSPF, ISIS, and emerging technologies like SR, SRv6, EVPN - Building and maintaining comprehensive automation infrastructure for Cisco's routing platforms - Debugging complex system-level issues and handling critical customer escalations with priority focus - Collaborating with cross-functional teams including Development, Hardware, Marketing, and Customer Teams in an agile environment Minimum Qualifications: - BE/B.Tech/ME/M.Tech in Engineering or related technical field - 7-12 years of hands-on experience in manual testing - Hands-on experience testing L2, L3, and MPLS protocols including OSPF, BGP, ISIS, MPLS LDP, L2VPN, L3VPN - Deep understanding of Service Provider deployment scenarios and networking technologies Preferred Qualifications: - Automation and programming test scenarios for networking products - Programming experience with Python and TCL/PERL languages - Cisco Networking certifications such as CCIE, CCNP, or equivalent professional certifications - Experience with emerging technologies including EVPN, SR, SRv6, VxLAN, IGMP, Multicast Routing, MVPN, SP QoS - Proven ability to work effectively in highly collaborative, inclusive, and agile team environments - Strong analytical and debugging skills for complex system-level issues and customer problem resolution - Advanced programming expertise in Python with honors, certifications, or demonstrated excellence - Developing robust test scenarios and frameworks using Python or TCL programming Join the SP Routing team at Cisco, where every individual brings their unique skills and perspectives together to pursue the purpose of powering an inclusive future for all. Our passion is connection, and we celebrate our employees" diverse backgrounds, focusing on unlocking potential and encouraging learning and development at every stage. We pioneer hybrid work trends, enabling everyone to give their best and be their best. At Cisco, we understand the outstanding opportunity we have to bring communities together, and at the heart of that are our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. We offer dedicated paid time off to volunteer, allowing us to give back to causes we are passionate about, with nearly 86% of employees taking advantage of this opportunity. Our purpose, driven by our people, makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. Every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can – do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Category Engineering Hire Type Employee Job ID 12379 Remote Eligible No Date Posted 28/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We’re Hiring – Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Required Skills: Proficiency in Floor Planning techniques. Expert practical experience with tools such as Innovus. Solid understanding of Fusion Compiler functionalities. Preferred Qualifications: Background in scripting languages including Tcl, Tk, or Perl. Knowledge of Physical Design workflows and methodologies. Previous experience working with advanced technology nodes (submicron, 28nm and below). Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹5,000,000.00 per year Schedule: Monday to Friday Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Background in scripting languages including Tcl, Tk, or Perl? Expert practical experience with tools such as Innovus? Experience working with advanced technology nodes (submicron, 28nm and below). Location: Vishakhapatnam, Andhra Pradesh (Preferred) Work Location: In person

We’re Hiring – Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Required Skills: Proficiency in Floor Planning techniques. Expert practical experience with tools such as Innovus. Solid understanding of Fusion Compiler functionalities. Preferred Qualifications: Background in scripting languages including Tcl, Tk, or Perl. Knowledge of Physical Design workflows and methodologies. Previous experience working with advanced technology nodes (submicron, 28nm and below). Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹5,000,000.00 per year Schedule: Monday to Friday Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Background in scripting languages including Tcl, Tk, or Perl? Expert practical experience with tools such as Innovus? Experience working with advanced technology nodes (submicron, 28nm and below). Location: Vishakhapatnam, Andhra Pradesh (Preferred) Work Location: In person

Job Title: Data Analytics Trainer Location: Shadnagar, Hyderabad Duration: 3 Months (400hrs) Job Summary We are seeking an experienced and passionate Data Analytics Trainer to deliver high-quality training in our 400-hour Data Analytics program, spanning 3 months. The ideal candidate will have deep expertise in Advanced Excel , Power BI , Tableau , MySQL , Python for Data Analysis , and foundational Machine Learning concepts. The trainer will facilitate both theoretical and practical sessions, guide students through hands-on projects, and prepare them for real-world data analytics challenges across domains like finance, healthcare, e-commerce, and more. Key Responsibilities Deliver Training Modules : Conduct engaging and interactive sessions covering the following: Advanced Excel (60 hours): Teach cell referencing, arithmetic/logical/lookup functions, data validation, pivot tables, charts, dashboards, and Power Query/Power Pivot. Power BI (66 hours): Guide students through data loading, visualization (column/line charts, conditional formatting), Power Query Editor, DAX expressions, and dashboard creation. Tableau (66 hours): Train on data visualization, filters, calculations (basic, LOD, table), custom charts, and dashboard actions, including Tableau Public integration. MySQL (60 hours): Instruct on SQL commands (DDL, DML, DQL, TCL), joins, indexes, views, stored procedures, triggers, and sub-queries. Python for Data Analysis (24 hours): Teach Python basics, data types, pandas for EDA, data visualization with matplotlib/seaborn, and data wrangling. Introduction to Machine Learning (72 hours): Cover statistics, hypothesis testing, EDA, linear/logistic regression, clustering, feature engineering, and model validation. CRT Training (54 hours): Facilitate sessions on quantitative aptitude, logical reasoning, verbal ability, and soft skills (e.g., presentation, teamwork, interview skills). Required Qualifications Education : Bachelor’s/Master’s degree in Data Science, Computer Science, Statistics, or a related field. Experience : 3+ years of professional experience in data analytics or data science. 1+ years of training or teaching experience in data analytics tools (Excel, Power BI, Tableau, MySQL, Python). Hands-on experience with machine learning concepts and Python libraries (pandas, matplotlib, seaborn). Technical Skills : Proficiency in Advanced Excel (VLOOKUP, INDEX-MATCH, Pivot Tables, Power Query). Expertise in Power BI (DAX, Power Query, dashboard creation) and Tableau (LOD calculations, custom charts). Strong knowledge of MySQL (joins, stored procedures, triggers) and Python (pandas, data visualization). Familiarity with machine learning concepts (regression, clustering, feature engineering). Soft Skills : Excellent communication and presentation skills. Ability to simplify complex concepts for beginners. Strong problem-solving and mentoring abilities. Preferred Qualifications Industry experience in domains like finance, healthcare, e-commerce, or supply chain analytics. Certifications in Power BI , Tableau , or Python (e.g., Microsoft Certified: Data Analyst Associate). Experience with capstone project mentoring in data analytics or machine learning. Familiarity with quantitative aptitude, logical reasoning, and soft skills training. Note : Mode of delivery is offline. Transportation and Accommodation will be provided.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description Job Description Ø Define and develop verification environments Ø Write verification plans, and documentation Ø Generate test bench and automatic regression plans Ø Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs Ø Complete block-level verification and chip level verification Ø Bring a self-motivated and enthusiastic approach that will achieve any new Ø requirements and overcome all challenges Ø Able to work mostly independently and handle complex SoC Verification platform. Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities Requirements/Qualifications Qualifications/Requirements Ø Minimum of 4 years related proven silicon design or verification work experience Ø Hands on project experience with leading edge verification methodologies like OVM/UVM Ø One of the Protocol knowledges AXI/AHB/DDR/PCIe is must Ø Hands on project experience in coverage/assertion driven verification Ø Knowledge of IC chip design, development flow, process, and methodology Ø Knowledge of CMOS logic design, circuit design, and circuit analysis Ø Proficient in HDL languages System Verilog, Verilog and VHDL Ø Good knowledge of UNIX shell scripting, Perl and TCL scripting. Ø Good knowledge and understanding of CMOS device operation and characteristics Ø Proven experience in writing verification plans and test bench development, simulation, and debugging Ø Proficient with UNIX environment, and CAE/CAD tools such as schematic capture, simulation, design verification Ø Must be able to learn new technology Ø Good analytical and problem-solving skills Ø Excellent written and verbal communication in English. Ø Experience dealing with and communicating at different levels of the organization Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience is also acceptable. The desired experience range for this role is 7 to 10 years. Key responsibilities include the physical design of block levels with a full understanding of the PnR cycle, a good grasp of Physical design fundamentals, and hands-on experience with industry-standard pnr tools like ICC2/Innovus. Additionally, familiarity with signoff tools such as Prime Time, Redhawk, and calibre is necessary. The candidate should possess the ability to guide junior engineers in resolving technical issues. Proficiency in tools like ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS, and scripting languages like TCL and Perl is required for this role. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information and proprietary data. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities at Qualcomm and is not to be used by staffing or recruiting agencies. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not respond to requests for application updates or resume inquiries through the provided email address. For further information about this role, please reach out to Qualcomm Careers.,

You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,

You will be joining onsemi's Image Sensors Group in Bengaluru, India as a Sr Analog Mixed Signal Verification Engineer. This group focuses on developing image sensors for various applications like industrial, consumer, and automotive. Your main responsibilities in this role include defining and implementing mixed-signal verification testcases, hands-on verification of Analog Mixed-Signal simulations, writing Analog Behavioral models, collaborating with cross-functional teams, employing scripting languages for automation, participating in silicon debug, and contributing to the team's success through active participation and effective communication. To qualify for this position, you should have expert-level knowledge in Analog Mixed-Signal simulations, proficiency in modeling Analog blocks using SV Real Modeling / Verilog-AMS /Verilog-A, experience in verifying ADCs and DACs, proficiency in scripting languages like PERL, TCL, Python, excellent communication skills, a collaborative mindset, and the ability to quickly adapt to new systems and processes. Minimum Requirements for this role include a BE in Electrical Engineering or related field with 6 years of experience, or an MS with 4 years of experience in AMS verification. onsemi, a company focused on automotive and industrial end-markets, is driving disruptive innovations to contribute to a better future. They are involved in megatrends such as vehicle electrification, safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a focus on creating intelligent power and sensing technologies, onsemi aims to solve complex challenges and pave the way for a safer, cleaner, and smarter world. Join a team committed to sourcing, attracting, and hiring high-performance innovators while providing a positive recruitment experience for all candidates, establishing onsemi as a great place to work.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

You are an experienced AMS Verification Engineer with over 8 years of expertise in AMS IC verification, possessing hands-on experience in VerilogAMS, SystemVerilog, and UVM. Your strong skills lie in VerilogAMS and Real Number Modeling, and you have a solid understanding of Cadence tools, VManager, and Tcl/Perl. Any knowledge or experience in Analog/RF would be considered a valuable advantage. The location for this position is in Bengaluru. If you believe you are a suitable candidate for this role, we encourage you to reach out by either sending a direct message or sharing your CV to aayushi.sharma@saracasolutions.com. Join us in shaping the future of semiconductors!,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

You will be part of a dynamic team that drives technology innovations shaping the way we live and connect, contributing to the Era of Pervasive Intelligence. In this role at Synopsys, you will work on high-performance silicon chips that play a crucial role in creating a healthier, safer, and more sustainable world. As an Apprentice, you will gain hands-on experience through real-world projects, collaborating with passionate teams globally and exploring cutting-edge technology. This is your chance to unleash your creativity, share your ideas, and bring solutions to life, shaping not only the future of innovation but also your own career path. Your responsibilities will include running QA and regression tests for developed Process Design Kits (PDKs), participating in PDK development for Synopsys customers, providing technical assistance for tool-related issues, and creating and delivering product training material. To excel in this role, you should be a graduate engineer (2023/2024) in Computer Science or Electronics with a solid understanding of circuit designs and related methodologies. Additionally, you should possess knowledge of CMOS fundamentals, familiarity with ASIC design flow and VLSI design methodologies, hands-on experience with UNIX/Linux, proficiency in scripting languages like Perl, Python, Tcl, strong debugging skills, and a passion for problem-solving. Effective communication skills and the ability to coordinate discussions in a small group are essential for success in this role. This 12-month Apprenticeship Program is based in Hyderabad and follows an on-site, full-time working model. The internship is set to start in May/June 2025. Synopsys is committed to fostering an inclusive culture where everyone can thrive, both professionally and personally. Join us in fueling today's innovations and sparking tomorrow's creativity as we work together towards our shared goals of Integrity, Excellence, Leadership, and Passion. Shape your future with us today!,

You will be a part of Cisco Networking Engineering (CNE) in India, a business unit focused on the development of High-End Routers and Optical products. Your role will involve delivering high-quality software solutions to ensure customer satisfaction and faster adoption. You will use your expertise to provide innovative product recommendations and solutions, with a deep understanding of Optical Technologies like DWDM, ROADM, OTN, and Coherent. As a part of the team, you will engage in end-to-end system/solution testing, debugging complex network issues, and working on network automation and analytics applications. Collaboration with global teams, customer interfacing, and stakeholder management will be key aspects of your role. Hands-on experience with Manageability Applications like OpenConfig, Restconf, Netconf-yang, and Telemetry is essential. You are expected to have excellent knowledge and testing skills in Optical technologies, along with experience in test engineering concepts, methodologies, and automation tools. Strong communication skills, problem-solving abilities, and a results-oriented mindset are required. A degree in EE/CS combined with 10-12 years of proven experience is preferred. Industry certifications such as CCNA/CCNP/CCIE/JCNA/JCIE will be advantageous. Cisco offers exciting career opportunities in the ever-evolving technology landscape. By joining Cisco, you will be part of a pioneering team driving innovation in areas like SP/Web, mobile, cloud, security, and big data. Embracing diversity and individuality, Cisco encourages you to be yourself and make a difference in the world of technology.,

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. As a member of the team, you will lead the design analysis and methodologies of various memory blocks, ensuring they meet over 5GHz frequency and low-power digital designs with optimal area utilization. Your role will involve a deep understanding of different memory design concepts such as SRAM, RF, and ROM along with expertise in static timing analysis concepts. Close collaboration with Layout and Floor planning teams will be essential for successful back end design implementation of new features. Additionally, you will specialize in memory post-silicon analysis and possess a good grasp of statistical variation. To qualify for this position, you must hold a master's degree in electrical or computer engineering with a minimum of 8 years of experience in the related field. Alternatively, a bachelor's degree with at least 10 years of experience will be considered. Technical expertise in synthesis, P and R tools is preferred for this role. Preferred qualifications include experience in digital design with a focus on high speed and low power, familiarity with Verilog/VHDL, and proficiency in Tcl, Perl, and Python scripting. A good understanding of spice simulations and analysis, custom circuit design, IO design, full chip clocking, and strong verbal and written communication skills are also desired. Previous experience in design and verification of high-speed clocks, hierarchical designs, and budgeting of latencies and skews will be beneficial. This role falls under the Experienced Hire category and is based in India, Bangalore. The Client Computing Group (CCG), responsible for driving business strategy and product development for Intel's PC products, is the primary business group for this position. CCG focuses on delivering purposeful computing experiences across various form factors such as notebooks, desktops, 2 in 1s, and all in ones, aiming to unlock people's potential through innovative products. The role will involve collaborating with industry partners to design and deliver a predictable cadence of leadership products, contributing to Intel's mission of enriching the lives of every person on earth. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change.,

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates. We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built—from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. 4 - 7 years of experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

We Are: Drive technology innovations that shape the way we live and connect Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world, Apprenticeship Experience: At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide?and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path Join us and start shaping your future today! Mission Statement: Our mission is to fuel todays innovations and spark tomorrows creativity Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive?both at work and beyond, What Youll Be Doing: Contribute towards developing IC Validator DRC, LVS, Fill and PERC runsets Collaborate with R&D team on technologies/solution roadmaps to help them focus on the most critical design challenges Work with other Synopsys field teams, ensuring overall consistency of IC Validator solutions and that they meet customer needs, What Youll Need: Should be a graduate engineer (2024/2025) in Electronic Engineering, Computer Science, Familiarity with physical verification tool like IC Validator, Calibre, PVS or any other PV tool Understanding of DRC, LVS, Fill and multi-patterning concepts Excellent problem-solving skills Understanding of physical design layouts Good knowledge of scripting languages like Python, TCL or Perl Key Program Facts: Program Length: 12 months Location: Hyderabad Working Model: On-site Full-Time/Part-Time: Full-Time Start Date: Aug/Sep 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws If you need assistance or a reasonable accommodation during the application process, please reach out to us, Show

Job Title - F5 iRules Scripting - TCL Total exp : 9 years to 13years Location -Mumbai,Pune,Chennai,Hyderabad, Bangalore,Noida,Kolkata (Pan India LTIM Location) Interview Mode : Virtual Notice Period : Immediate Joiner JD: The Senior ADC Migration Engineer will be responsible for the endtoend migration of complex Application Delivery Controller ADC configurations from Citrix NetScaler to F5 BIGIP platforms A key focus of this role will be the expert analysis translation and reimplementation of custom Citrix LUA scripts into equivalent F5 iRules Tcl and leveraging other F5 native features This role requires deep technical expertise in both Citrix NetScaler and F5 BIGIP along with strong scripting and problemsolving abilities. Key Responsibilities: Discovery and Assessment Conduct thorough analysis of existing Citrix NetScaler configurations including Virtual Servers Services Policies Profiles and custom LUA scripts to understand their functionality and dependencies LUA Script to iRule Translation Expertly analyze complex Citrix LUA scripts and translate their functionality into optimized F5 iRules Tcl or alternative F5 features eg Local Traffic Policies data groups Access Policy Manager profiles where appropriate Configuration Migration Design configure and implement equivalent F5 BIGIP configurations primarily focusing on LTM Local Traffic Manager and APM Access Policy Manager objects Policy and Profile Conversion Map and convert Citrix policies eg rewrite responder content switching and profiles eg HTTP SSL to their F5 counterparts Testing and Validation Develop and execute comprehensive test plans to ensure functional parity and optimal performance postmigration including load testing and security validation Documentation Create detailed documentation of migrated configurations iRules and architectural changes Troubleshooting Diagnose and resolve complex issues arising during the migration process and postmigration Collaboration Work closely with application owners network architects security teams and project managers to ensure seamless migration and minimal business disruption Best Practices Advocate and implement F5 best practices for security performance and maintainability Mentorship Potentially mentor junior team members on F5 BIGIP technologies and migration strategies Required Skills and Qualifications Education Bachelors degree in Computer Science Information Technology or a related field. Experience : Minimum of 7 years of handson experience with Application Delivery Controllers ADCs Extensive experience 5 years with Citrix NetScalerADC platforms including advanced configuration policy creation and expertlevel proficiency in Citrix LUA scripting Extensive experience 5 years with F5 BIGIP platforms including LTM and strong proficiency in F5 iRules Tcl Experience with APM is highly desirable Demonstrable experience in successfully migrating ADC configurations between different vendor platforms Citrix to F5 preferred Technical Proficiency Deep understanding of networking protocols TCPIP HTTPS DNS SSLTLS Strong command of Tcl scripting language for iRules development Strong understanding of security concepts related to ADCs SSL offloading authenticationauthorization Familiarity with automation tools and scripting eg Python Ansible for ADC configuration management is a plus Knowledge of payment industry protocols such as GICC and POSrelated protocols is a significant advantage

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience, 5 years of experience in physical design, 5 years of experience in static timing analysis, circuit/signoff methodology and simulation, Experience in one or more sign-off convergence in Static timing analysis (STA) electrical checks and physical verification domains, Preferred qualifications: Experience in using Static Timing Analysis (STA), power grid network delivery, and power analysis tools, Experience in timing signoff for SoCs or designs with multiple voltage/clock domains, Experience with Exploratory Data Analysis (EDA) tools for implementation and signoff, Physical Design, Static Timing Analysis (STA) and Electromigration and IR drop (EMIR) analysis, Experience in automation with programming in TCL, Python, Perl and the knowledge of Speed path debug or correlation studies, About the jobGoogle's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world, Responsibilities Work with post-silicon validation teams to improve and debug speed, Vmin and yield related issues, Work with cross-functional teams circuit design, physical design and sign-off methodology teams, Explore and specify new circuit/Static Timing Analysis methodologies for better polycrystalline silicon photovoltaic modules for low-power subsystems/System on a Chip (SoCs), Work with the testchip teams on process nodes to build, validate and characterize custom Internet Protocols (IPs), Build automation for circuit methodology, simulation and analysis, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. The Opportunity We’re looking for a QA Lead in Routing & Switching testing along with python Automation in Gurugram to help validate and accelerate the performance of our Routing & Switching platforms. If you thrive in network testing, Python automation, and Layer 2/3 protocols, you’ll feel right at home here. You’ll lead the validation of our next-gen networking platforms—designed for the world’s leading service providers. From our state-of-the-art R&D labs in Gurugram to live Tier-1 deployments worldwide, you’ll work on cutting-edge technology that powers the world’s leading service providers, while growing your own expertise. Roles And Responsibilities Design, develop, and automate test strategies for Routing & Switching products, with a focus on platform-independent software features. Build Python-based automation to validate Layer 2/3 protocols (e.g., BGP, IS-IS, BFD, QoS, MPLS, EVPN, VPLS, VPWS). Define and execute test plans, develop test cases, and lead system-level validation using tools like Ixia and Spirent. Set up complex testbeds, troubleshoot issues, and collaborate with development teams on defect resolution. Review test cases, feature specs, and provide technical input during design and implementation phases. Ensure compliance with commercial specs, RFCs, and real-world network topologies. Document test results and automate reporting using Quality Center (QC) or equivalent tools. Actively contribute to agile scrum teams, ensuring timely delivery of production-ready features. Share knowledge across teams, mentor junior engineers, and lead knowledge-sharing sessions. Role Requirements 6 to 10 years of experience in QA/Testing for networking systems—especially in Routing & Switching. Deep understanding of L2/L3 topologies, network switches, and data communication systems. Strong hands-on experience with: Python, Tcl/Expect for test automation Traffic generators (Ixia, Spirent) Protocols: BGP, IS-IS, BFD, QoS, RSVP-TE, EVPN, VPLS, VPWS Bachelor’s or Master’s degree in Electronics, Communication, or Computer Science. Bonus if you have experience with Netconf, GNMI, and Telemetry. Why Ciena We’re a global leader in high-speed connectivity, and our Gurgaon R&D center is a core innovation hub driving that mission forward. Here’s What Makes Us Different Real-World Impact: Our work powers the world’s largest networks—from 5G rollouts to cloud data centers—giving you the opportunity to see your contributions in live deployments. Depth of Technology: You’ll collaborate with industry leaders in Routing, Switching, SDN/NFV, and automation, solving complex challenges at scale. Learning Culture: With cutting-edge labs, continuous learning, and exposure to next-gen technologies, you’ll keep growing your expertise alongside some of the best minds in networking. People-First: We champion flexibility, well-being, and belonging—offering a work environment where you can thrive both personally and professionally. Global Collaboration: Join a diverse team that spans continents but works as one to shape the future of connectivity. If you’re ready to push boundaries and grow your career in network QA and automation, Ciena is where your skills will make an impact. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Gurugram, Haryana, India Department Sales Job posted on Jul 29, 2025 Employment type Employee We are looking for a detail-oriented and proactive Sales Analyst to join our growing APAC team. This role plays a critical part in supporting the APAC API Team and operations functions by monitoring credit compliance, analyzing booking and revenue trends, resolving key partner issues, and assisting with administrative processes. The ideal candidate should have strong analytical skills, excellent attention to detail, and the ability to coordinate across multiple teams and stakeholders. Key Responsibilities: Credit & Account Monitoring Monitor daily remaining credit for each client and track temporary credit limit (TCL) expiration to ensure compliance and uninterrupted service. Performance & Trend Analysis Conduct daily Net Revenue Margin (NRM) analysis across all clients and provide data-driven suggestions for optimization. Evaluate daily and weekly client booking trends to detect patterns, investigate client drop-offs, and report findings. Track search and error trends, highlighting anomalies for prompt investigation and resolution. Data Coordination & Administrative Support Support mapping file management and data coordination in collaboration with the Customer Success Team. Perform administrative tasks including: Client agency account creation Coordinating with the KYC and Finance Support teams to facilitate credit setup and live credential release Operational Issue Resolution Assist in resolving operations-related disputes, particularly with external partners such as big OTAs, in coordination with internal stakeholders. Refund Support Act as support for refund processing – reviewing cases and ensuring timely updates on refund status. Qualifications & Requirements: Bachelor’s degree in Business, Finance, Economics, or a related field 2–4 years of experience in sales operations, data analysis, or financial coordination Proficient in Microsoft Excel and data analytics tools (e.g., Power BI, Tableau is a plus) Strong attention to detail with an analytical and investigative mindset Ability to multitask, prioritize, and manage time effectively Good communication and coordination skills across internal and external teams

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa We want you to help us build on the success of our first generation of ML accelerator at edge, Work hard Have fun Make history, We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production, As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp, Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation, Own DFT planning, milestone tracking, and cross-functional checklist reviews, Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists, Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate, Education BASIC QUALIFICATIONS BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field, Experience 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT, Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production, DFT Architecture Expertise Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality, MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration, IEEE 1149 x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures, DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths, RTL and gate-level debug, including mismatch triage and simulation correlation, Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation, Tool Proficiency Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling, DFT logic insertion, pattern generation, and diagnostics, Design Background Experience in writing verilog/system verilog RTL related to DFT logic design, ATE Test Readiness Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets, Pattern validation, format conversion, and debugging across wafer sort and final test, Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements, Silicon Debug Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis, Automation Skills Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl, Collaboration Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing, Execution Excellence Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success, Leadership PREFERRED QUALIFICATIONS Led multi-site/global DFT teams, mentoring engineers and managing design reviews, Drove design-for-test planning in collaboration with customers or design services partners, Technical Depth Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies, Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues, Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement, Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037331 Show