1597 Tcl Jobs - Page 25

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

We are looking for a hands-on validation engineer who can convert real customer use cases into executable test plans (manual & automated), drive continuous product improvement, and work closely with cross-functional global teams. You Have: Graduate or Masters in engineering with 4 plus of experience in programming in automation/scripting languages like Python, Robot, Tcl or Perl. Exposure to Robot framework preferred Experience in testing NMS/EMS products, Cloud based solutions Worked with traffic tools like Spirent, Ixia or Router tester for end-to-end traffic testing It would be nice if you also have: Understanding of PON technology, solid knowledge of L2 switching architecture and most (or some) of protocols in the domain of Ethernet, VLAN handling, MAC handling, ARP, DHCP, IGMP, 802.1x, QoS, LLDP-MED, PoE. Work closely with our partners and end customers and assist in capturing their detailed requirements and their exact use cases. Translate this information into E2E validation test scenarios and test plans (with manual and automated tests). Execute on these E2E test plans, create fault reports and drive for proper fixes. Continuously drive for product improvements, by using your in-depth technical knowledge to improve and finetune existing technical customer documentation and collaterals for our partners. Work closely with R&D, PLM, and other functional teams to align validation activities with product goals. Learn and apply advanced tools and protocols such as PON, L2 switching, QoS, and validation tools like Spirent/Ixia.

Job Requirements Key Responsibilities: Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production. Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets. Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness. Define and implement test strategies for analog and mixed-signal IPs , including DFT hooks, wrappers, and test mode integration. Create test patterns and perform ATPG analysis to ensure test coverage goals are met. Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams. Automate and optimize DFT flows and scripting for scalability and efficiency. Required Qualifications: B.E./B.Tech or M.E./M.Tech in Electrical Engineering or related discipline. Minimum 10 years of hands-on experience in DFT with successful tapeouts. Strong knowledge of scan insertion , scan compression , transition fault (at-speed) testing , and boundary scan (IEEE 1149.1/1500). Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired. Experience with ATPG tools , test coverage analysis, and test pattern generation. Solid understanding of DFT for AMS blocks , including challenges in testability of analog circuits. Familiarity with scripting languages (TCL, Perl, Python) for automation. Good understanding of STA constraints for DFT and impact on synthesis and physical design. Proven experience in silicon debug and production test support Work Experience Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired. Experience with ATPG tools , test coverage analysis, and test pattern generation. Solid understanding of DFT for AMS blocks , including challenges in testability of analog circuits. Familiarity with scripting languages (TCL, Perl, Python) for automation. Good understanding of STA constraints for DFT and impact on synthesis and physical design.

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor’s or Master’s degree in Electronics 4–8 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities

Looking for Siemens EDA ambassadors: PowerPro PV/CAE for Power Estimation /Optimization We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us - whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by increasing efficiency and customer happiness Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: Calypto System Design "Central Engineering Group (CEG)" group. CSD works on cutting edge tools like PowerPro, Catapult etc. The Product Validation and Customer Support team of CEG ensures quality products, educated and satisfied customers in the market for High Level Synthesis. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Work on different methodology for customer scenario. Provide script-based solution for quick turnaround time. Work on RTL to GDS flow , Glitch, Veloce PowerPro, PowerPro optimization flows. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, RTL to GDS flow expertise, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Strong Debugging Skills is must. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Knowledge of different tools like (DC, Fusion compiler, RTL Architect, Prime Power, Prime time, Zebu, joules, Gate sign off tools etc ) Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. We’ve got quite a lot to offer. How about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Accelerate transformation #li-eda #li- Hybrid

Key Responsibilities: Perform high-quality mesh generation for structural analysis using Hypermesh and Patran. Develop and refine GFEM and DFEM models for various components and assemblies, ensuring mesh quality and compliance with CAE standards. Prepare models for static, dynamic, and thermal FEA simulations. Interpret and apply engineering drawings and CAD data to build accurate finite element models. Ensure mesh quality and convergence to meet analysis requirements. Ensure adherence to customer-specific FEM guidelines and industry best practices. Collaborate closely with design, simulation, and test teams to validate and iterate FE models. Document meshing processes, model assumptions, and preprocessing methodologies. Troubleshoot and resolve issues related to meshing and model setup. Familiarity with optimization techniques for FE modeling. Required Skills & Qualifications: Bachelor's or Master's degree in Mechanical, Aerospace, or related engineering field. 3 to 7 years of relevant CAE experience, with a focus on meshing and preprocessing. Strong command of Hypermesh and Patran for shell and solid meshing. Hands-on experience in GFEM and DFEM meshing techniques and standards. Solid understanding of FEA fundamentals, material properties, and boundary conditions. Familiarity with CAD software (e.g., CATIA, NX) for model extraction and cleanup. Excellent problem-solving and communication skills. Ability to manage multiple tasks and meet tight deadlines. Proactive attitude towards continuous improvement and learning. Preferred: Exposure to solver environments like OPTISTRUCT, NASTRAN, ABAQUS for FE model set-up Experience with scripting or automation (e.g., TCL, Python) in preprocessing. Knowledge of aerospace or automotive domain-specific CAE workflows.

Mandatory Skills: TypeScript TCL/TK Secondary/Alternate Skills: Java Full Stack Development Job Description: Minimum 2+ years of total experience with 1–2 years relevant experience in TypeScript and TCL/TK. Hands-on expertise in developing and maintaining applications using TypeScript and TCL/TK . Exposure or working knowledge of Java Full Stack is a strong advantage. Should be comfortable working onsite from Day 1 at the Mysuru location. Must be available for Face-to-Face interview at IBM Mysuru office when requested. Ability to work independently and collaboratively in a dynamic team environment. Strong problem-solving and debugging skills with a focus on delivering high-quality code.

This is a full-time on-site role for a Standard Cell & Memory Characterization Engineer located in Hyderabad. The Engineer will be responsible for the day-to-day tasks of developing standard cells and memory characterization methodologies, performing detailed analysis and verification, conducting research, and working with wireless technologies. The role requires a collaborative approach to problem-solving and a commitment to quality and precision in delivering engineering solutions. STD Cell Characterization (PrimeLib, Silicon Smart) Able to characterize basic standard cells. Static & Timig Analysis of SRAM and DRAM. Writing constraints and analysing the STA report. Reporting violations to design team. STA at block/top/cell level .lib QA, ARC files, timing constraints DRAM circuit/block-level analysis Parasitic extraction, tape-out support EDA Tools: Synopsys, Cadence, TCL, Python

Job Details Description At Visteon, the work we do is both relevant and recognized—not just by our organization, but by our peers, by industry-leading brands, and by millions of drivers around the world. That’s YOUR work. And, as a truly global technology leader in the mobility space, focused on building cross-functional AND cross-cultural teams, we connect you with people who help you grow. So here, whatever we do is not a job. It’s a mission. As a multi-billion-dollar leader of disruptive change in the industry, we are shaping the future, while enabling a cleaner environment. No other industry offers more fast-paced change and opportunity. We are in the midst of a mobility revolution that will completely change the way we interact with our vehicles, reduce the number of car accidents and fatalities, and make the world a cleaner place. Visteon is at the epicenter of this mobility revolution. Two major trends in the automotive industry – the shift to electric vehicles and vehicles with autonomous safety technologies – have created unique opportunities for Visteon. We are the only automotive provider focused exclusively on cockpit electronics – the fastest-growing segment in the industry. Bachelor’s degree in Engineering (Electrical/Electronics - Master’s preferred) 10+ Years of Experience in the embedded Systems Development, preferably in the field of Automotive SW-HW co-development and HSIS Verification. Expertise in the ability / understand to read HW Schematics, handling Gerber files, reading datasheets, errata's and application notes from silicon vendors. Expertise in testing communication and memory buses like CAN, LIN, Ethernet, I2C, SPI & eMMC Expertise in scripting languages such as python, Lua, TCL etc., Hands-on experience in handling sensitive electronic equipment in a EMC safe environment. Experience with test automation framework such as Robot Framework is desirable Good programming knowledge in basic C/C++ and understanding of HW/SW architectures. Tools: Logic Analyzer, CANalyzer, Function Generators and Debugger tools (TRACE32/Lauterbach) Experienced in Agile/SCRUM terminologies SW Development Lifecycle understanding, HSIS Defects triaging and management Experienced in handling multiple projects simultaneously to completion More Good Reasons to Work for Visteon Focusing on the Future Our company strategy focuses on leading the evolution of automotive digital cockpits and safety solutions. This strategy is driven by constant innovation, and you will support our efforts through your role. We are recognized across the industry for innovation. We have a strong book of business that is expected to drive future growth, along with a customer base that includes almost every automotive manufacturer in the world. Company Culture Working at Visteon is a journey in which our employees can develop their strengths and advance their careers while making a difference globally. Join us and help change the world and how we interact with our vehicles. Visteon is where the best technical talent creates the future. Learn more about our culture here. About Visteon Visteon is a global technology company serving the mobility industry, dedicated to creating a more enjoyable, connected and safe driving experience. The company’s platforms leverage proven, scalable hardware and software solutions that enable the digital, electric, and autonomous evolution of our global automotive customers. Visteon products align with key industry trends and include digital instrument clusters, displays, Android-based infotainment systems, domain controllers, advanced driver assistance systems and battery management systems. The company is headquartered in Van Buren Township, Michigan, and has approximately 10,000 employees at more than 40 facilities in 18 countries. Visteon reported sales of approximately $2.8 billion and booked $5.1 billion of new business in 2021.Learn more at www.visteon.com. Follow Us For more information about our company, technologies and products, follow us on LinkedIn, Twitter, Facebook, YouTube and Instagram. You can also follow our careers-focused channels on Twitter and Facebook to keep up with our latest job postings and the great work our employees are doing.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI. Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 14 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. Arista is a well-established and profitable company with over $7 billion in revenue. Arista’s award-winning platforms, ranging in Ethernet speeds up to 800G bits per second, redefine scalability, agility, and resilience. Arista is a founding member of the Ultra Ethernet consortium. We have shipped over 20 million cloud networking ports worldwide with CloudVision and EOS, an advanced network operating system. Arista is committed to open standards, and its products are available worldwide directly and through partners. At Arista, we value the diversity of thought and perspectives each employee brings. We believe fostering an inclusive environment where individuals from various backgrounds and experiences feel welcome is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as the Great Place to Work Survey for Best Engineering Team and Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest quality and performance standards in everything we do. Job Description Who You’ll Work With You will work as Software Tools Development Engineer for the Hardware Team.We design virtually all of the hardware and software that goes into our products, and it’s a badge we wear proudly. This wouldn’t be possible without the likes of talented engineers who are given the opportunity to fully lead their own projects and the freedom to think outside the box.Individuals will work closely with part-time and dedicated multi-disciplinary engineers to create tools to hone Arista’s hardware development workflow with an eye toward improving quality and delivering the best possible products to our customers. What You’ll Do Candidates for this position would be responsible for the entire unit software design process: Authoring stress tests to validate hardware conceptual designs Authoring Functional Specifications to communicate intentions with the broader team Debugging of challenging issues multi-server execution environments Reviewing peers’ code against good-practices and target architectures Unit-test code development for validation (positive and negative testing) or new tests created Development of doc templates and test reports to communicate with hardware team counterparts of testing results Root-cause unexpected issues and develop multi-layered patches to address immediate and long-term consequences of the issue Drive your own efforts to contribute to hardware tools team overall priorities Learn the varied code languages to support the various tools used by existing team development software suites, including C/C++, golang, python, TCL, and others. Qualifications B.S. Electrical Engineering and/or B.S. Computer Engineering 3-5 years of relevant experience in software engineering for tools development Self-motivated w/ a passion for developing “elegant”, high-quality software solutions A strong curiosity supporting continuous learning and self-development Great communication skills and team-driven mindset Experience working with large software ecosystems utilizing CI/CD workflows Knowledge working with multi-processor clusters and computing environments Fundamental knowledge of networking protocols and operation Enthusiasm to work collaboratively with a multidisciplinary team to achieve a greater overall solution. Additional Information Arista stands out as an engineering-centric company. Our leadership, including founders and engineering managers, are all engineers who understand sound software engineering principles and the importance of doing things right. We hire globally into our diverse team. At Arista, engineers have complete ownership of their projects. Our management structure is flat and streamlined, and software engineering is led by those who understand it best. We prioritize the development and utilization of test automation tools. Our engineers have access to every part of the company, providing opportunities to work across various domains. Arista is headquartered in Santa Clara, California, with development offices in Australia, Canada, India, Ireland, and the US. We consider all our R&D centers equal in stature. Join us to shape the future of networking and be part of a culture that values invention, quality, respect, and fun.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

Looking for Siemens EDA ambassadors: PowerPro PV/CAE for Power Estimation /Optimization We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us - whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by increasing efficiency and customer happiness Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: Calypto System Design "Central Engineering Group (CEG)" group. CSD works on cutting edge tools like PowerPro, Catapult etc. The Product Validation and Customer Support team of CEG ensures quality products, educated and satisfied customers in the market for High Level Synthesis. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Work on different methodology for customer scenario. Provide script-based solution for quick turnaround time. Work on RTL to GDS flow , Glitch, Veloce PowerPro, PowerPro optimization flows. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, RTL to GDS flow expertise, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Strong Debugging Skills is must. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Knowledge of different tools like (DC, Fusion compiler, RTL Architect, Prime Power, Prime time, Zebu, joules, Gate sign off tools etc ) Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. We’ve got quite a lot to offer. How about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Accelerate transformation Hybrid

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience : 7 to 15 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools : ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS Scripting: TCL, Perl Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076457

Responsibilities: • Support network functionality including Load Balancers, Firewalls, monitoring, and mitigation devices. • Design, Development and Support of systems used to automate network deployment and operational management processes across both cloud and enterprise networks. • Validate existing systems and recommend changes to optimize the design and performance of network automation and management systems. • Use Automation and Management Systems to collect data, provide reports & dashboards and deploy changes to the production network. • Automate the existing/new features using TCL / Python / Robot frame works is desirable. • Use DevOps principles to script and automate workflows, testing for Network Security Operations • Draft network diagrams, perform network planning and implement changes. • Resolve critical security and network issues. • Continuously refine processes and procedures with a focus on standardizing the work and shifting it to lower-level support teams • Take ownership and work independently on problems and handle escalations from Operations. Required Skillsets: • 8+ years of relevant experience working in NOC environment would be an added advantage. • Must be familiar with L2/L3 network device function, configuration, and protocols (VLAN, TCP/IP, DHCP, IPv4, etc). • Familiarity with common industry test equipment (Cisco Switches/Routers, IXIA traffic generator etc.) is required. • Advance knowledge on F5 Load Balancers platforms for application delivery and a deep understanding of network design • Experience building and maintaining firewalls & load balancers and similar network functionality through automation software (e.g. Docker, Kubernetes, Ansible) • Experience developing operational tools using Python and / or related languages. • Strong desire to code and good understanding of Software Development standard methodologies, open-source systems, and familiarity with Git repositories • Experience with NMS protocols, data structures and modelling (Rest API, Jinja) • Thorough troubleshooting, problem solving and analytical skills including packet capture analysis. • Familiarity with monitoring tools such as (ELK/Logstash, Grafana, Loggly) and packet trace analysis tools (e.g. tcpdump, NetworkMiner, wireshark) • Analytical thinker with strong attention to detail Exp: 8 + Years: • Excellent customer service skills together with experience in banking Industry • Drive Major incidents calls independently and keep the communication channel updated. • Good understanding of ITIL methodology, in-depth knowledge in incident, change and problem management process. • Good communication skills and should be a great team player. • CCNP / Palo Alto / Checkpoint / F5 / CCIE / CCSE – Security would be an added advantage.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum Educational Qualifications: B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 10+ years of experience in physical design using industry EDA tools. Lead Sub System/SOC physical design for at least 1 product. Experience in Python/Perl/TCL programming languages. Experience in signoff domains (timing, IR-RV. Power, Layout Verification) is an added advantage. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum Educational Qualifications: B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 5+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum Educational Qualifications: B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Position: Senior Memory Design Engineer Location: Bangalore / Noida Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS Transistors, their behaviors. Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit design. Expected to have good interpersonal skills. Minimum 2 Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/TCL/Python. Some Experience of working on Cadence or Synopsys flows. Experience with Circuit Simulation and Optimization of standard cells. Interested candidates can apply/share/refer profile at Krishnaprasath.s@acldigital.com

Exp: 3 to 15 Yrs Location: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamenta lsHands on experience in System Design with FPGA devices with relevant FPGA EDA too lsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPG AsWrite high quality code in Verilog/System Verilog, VHDL and C code for embedd edprocessors. Maintain existing cod e.Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/V IPExperience in using Synthesis, Placement constrain tsSTA constraint definition and Timing closure for high speed desig nsValidation of FPGA based implementation on HW boa rdExperience in writing embedded FW programs in C/C ++Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debugge rsBe conversant with on-chip debug too lsExperienced with scripting tcl/pe rlExposure to Version management systems, GitHub, S VNExcellent verbal and written communication skills in Engli shStrong technical background in silicon validation, failure analysis and deb ugUnderstand hardware architectures, use models and system level design implementations required to utilize the silicon feature s.

Job Title: Lead FPGA Design Engineer Experience Required: 6+ years Location: Hyderabad/Bangalore Job Type: Full-time Industry: Semiconductor / Electronics / Embedded Systems Job Summary: We are looking for a highly skilled and experienced Lead FPGA Design Engineer to join our hardware design team. The ideal candidate will lead the design, implementation, verification, and validation of FPGA-based systems for complex hardware products. This role involves mentoring junior engineers, collaborating with cross-functional teams, and ensuring delivery of high-performance, high-reliability designs. Key Responsibilities: Lead architecture definition and design of complex FPGA solutions using VHDL/Verilog/SystemVerilog. Translate system-level requirements into FPGA design specifications. Hands-on implementation of FPGA designs using Xilinx, Intel (Altera), or Lattice FPGAs. Develop testbenches and perform simulation using tools like ModelSim, Questa, or VCS. Integrate and validate FPGA designs on hardware, working closely with board design and software teams. Use industry-standard tools such as Vivado, Quartus, Synplify, etc. Lead FPGA timing closure, floor planning, and resource optimization. Perform version control, documentation, and design reviews. Guide and mentor a team of junior engineers; ensure design best practices and quality processes are followed. Required Skills and Experience: Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering. 6+ years of industry experience in FPGA design and verification. Expertise in VHDL/Verilog/SystemVerilog coding and simulation. Experience with FPGA toolchains such as Xilinx Vivado, Intel Quartus, Synplify. Strong knowledge of high-speed interfaces (e.g., PCIe, DDR, Ethernet, AXI). Familiar with embedded processor systems (MicroBlaze, Nios II, ARM SoCs). Proficiency in scripting (Tcl, Python, Shell) for automation. Experience with static timing analysis, constraints definition (SDC), and debugging. Good understanding of hardware/software integration. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications: Prior experience in leading FPGA teams or projects. Exposure to safety-critical or mission-critical design environments (e.g., automotive, aerospace, medical). Experience with hardware emulation or ASIC prototyping on FPGAs. Familiarity with version control systems (Git, SVN) and documentation tools. Why Join Us? Work on cutting-edge FPGA designs in a collaborative environment. Competitive compensation with leadership opportunities. Growth-focused, innovation-driven engineering culture. Interested can share CV to sharmila.b@acldigital.com