934 Tcl Jobs - Page 2

The HiLabs Story HiLabs is a leading provider of AI-powered solutions to clean dirty data, unlocking its hidden potential for healthcare transformation. HiLabs is committed to transforming the healthcare industry through innovation, collaboration, and a relentless focus on improving patient outcomes. HiLabs Team Multidisciplinary industry leaders Healthcare domain experts AI/ML and data science experts Professionals hailing from the worlds best universities, business schools, and engineering institutes including Harvard, Yale, Carnegie Mellon, Duke, Georgia Tech, Indian Institute of Management (IIM), and Indian Institute of Technology (IIT). Responsibilities Interpret business requirements, define technical alternatives, and participate in information gathering for interface requirements Develop, test, implement and document the technical solution to address the defined business requirements Develop and implement EDI HL7 and XML interfaces in accordance to Department Process/Standards Configuration and maintenance of Global Monitor and Security Work with other team members to define effort estimates, timetables, and project plans Participate with the development team and IT staff as appropriate in the design of solutions Educates and directly interacts with stakeholders to help them understand the benefits and limitations of their specific EMR/LIS-Interface during implementation Collaborate with other technical areas to integrate across tiers, platforms, and Responsibilities Ensure that expected application performance levels are achieved Plans and conducts module and basic integration testing Manage technical aspects of application to ensure timely and effective implementations Understand and comply to Project Life Cycle Methodology in all planning steps Responsible for multiple implementations or conversion projects Provides direct interaction with client and client’s vendor Designs and oversees interface implementation project plan Desired Profile Bachelor’s degree in appropriate discipline is preferred Cloverleaf Level 2 Certified 5 or more years of relevant experience is considered an experienced and seasoned professional Extensive experience with Cloverleaf Integration Services Experience building CCDA, VRL, HL7v2 ,HL7 FHIR (JSON) interface in CL 19.*v and beyond Knowledge on HL7 standards (v2,CDA, FHIR) Experience with VM-based Unix/Linux platforms Experience with data formats including HL7, XML, JSON Knowledge of scripting languages including TCL, TDOM programming, Java, JavaScript, experience in building webservice, Restful API interfaces Knowledge of Clinical integrations Experience working on Cloverleaf Consolidator (ICC) Tool Strong experience with a commercial Integration Engine Product (i.e., Cloverleaf) Experience using Jira Experience with HIE and integration platforms used within the health services industry (e.g., InterSystems, Medicity, Orion, etc.) Relevant experience in a healthcare setting working with the following HL7 transaction sets: ADT, VXU, ORM, MDM, SIU Familiarity with relational & non-relational databases such as MySQL, Postgres, Oracle, SQL Server, Mongo DB, Cassandra, IRIS/Caché Experience working in Agile development team Experience with SFTP is preferred CCPA disclosure notice - https://www.hilabs.com/privacy HiLabs Total Rewards Competitive Salary, Accelerated Incentive Policies, H1B sponsorship, Comprehensive benefits package that includes ESOPs, financial contribution for your ongoing professional and personal development, medical coverage for you and your loved ones, 401k, PTOs & a collaborative working environment, Smart mentorship, and highly qualified multidisciplinary, incredibly talented professionals from highly renowned and accredited medical schools, business schools, and engineering institutes. CCPA disclosure notice - https://www.hilabs.com/privacy Show more Show less

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description PostgreSQL Database admin Proficient with Postgres installation and configuration, particularly Postgres Plus Advanced Server from EnterpriseDB and AWS RDS Aurora PostgreSQL. Proficient with Postgres monitoring and alerting tools/processes, specifically PEM from EnterpriseDB. Proficient in the setup, configuration, and monitoring of PostgreSQL binary and logical data replication solutions (Binary Streaming, XDB, Bi-Directional Replication - BDR, etc.). Proficient with collecting diagnostics and tuning PostgreSQL as well as SQL tuning. Proficient with Postgres procedural languages (PL/pgSQL, PL/Tcl, PL/Perl, PL/Python) and SQL. Proficient in designing and supporting Postgres clustered environments. Monitoring and observability with tools like Splunk and Dynatrace. Experience in Postgres replication technologies. Perform debugging, tuning, and performance enhancement, as well as automation of operational and continuous integration aspects of the Postgres platforms. Proficient with the Linux operating system, specifically Oracle Linux Enterprise. Intermediate understanding of logical and physical data models.E Exp - 10 + years CBR - 130K Location - pune Notice - Immediate ͏ Do Provide adequate support in architecture planning, migration & installation for new projects in own tower (platform/dbase/ middleware/ backup) Lead the structural/ architectural design of a platform/ middleware/ database/ back up etc. according to various system requirements to ensure a highly scalable and extensible solution Conduct technology capacity planning by reviewing the current and future requirements Utilize and leverage the new features of all underlying technologies to ensure smooth functioning of the installed databases and applications/ platforms, as applicable Strategize & implement disaster recovery plans and create and implement backup and recovery plans Manage the day-to-day operations of the tower Manage day-to-day operations by troubleshooting any issues, conducting root cause analysis (RCA) and developing fixes to avoid similar issues. Plan for and manage upgradations, migration, maintenance, backup, installation and configuration functions for own tower Review the technical performance of own tower and deploy ways to improve efficiency, fine tune performance and reduce performance challenges Develop shift roster for the team to ensure no disruption in the tower Create and update SOPs, Data Responsibility Matrices, operations manuals, daily test plans, data architecture guidance etc. Provide weekly status reports to the client leadership team, internal stakeholders on database activities w.r.t. progress, updates, status, and next steps Leverage technology to develop Service Improvement Plan (SIP) through automation and other initiatives for higher efficiency and effectiveness ͏ Team Management Resourcing Forecast talent requirements as per the current and future business needs Hire adequate and right resources for the team Train direct reportees to make right recruitment and selection decisions Talent Management Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness Build an internal talent pool of HiPos and ensure their career progression within the organization Promote diversity in leadership positions Performance Management Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below Employee Satisfaction and Engagement Lead and drive engagement initiatives for the team Track team satisfaction scores and identify initiatives to build engagement within the team Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team Exercise employee recognition and appreciation ͏ Deliver No Performance Parameter Measure 1 Operations of the tower SLA adherence Knowledge management CSAT/ Customer Experience Identification of risk issues and mitigation plans Knowledge management 2 New projects Timely delivery Avoid unauthorised changes No formal escalations ͏ Mandatory Skills: PostgreSQL Database Admin. Experience: 5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description Physical Deisgn Lea Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure. ͏ Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities ͏ 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for ‘will’ based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation ͏ Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) ͏ Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the enhancement and evolution of GPU verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification reviews, suggesting improvements where necessary. About You Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Demonstrated experience in developing verification environments for complex RTL designs. Strong understanding of constrained-random verification methodologies and the challenges of achieving verification closure. Ability to define verification requirements, determine implementation approaches, and design testbenches. Expertise in root-cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. Experience managing multiple projects simultaneously. Strong communication skills for effectively conveying technical issues, both verbally and in writing. You might also have: Experience leading teams. Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Understanding of functional safety standards such as ISO26262. Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com. Show more Show less

Role Description Role Proficiency: Provide leadership to a project with appropriate technical options and well suited design standards for embedded system product development system level validation and performance optimization strategies. Outcomes Design develop and implement system level specifications. Develop highly optimized secured code debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP owners product (HW & SW) architects for design and debugging as per the project needs. Prepare Release Notes and participate in release strategies. Mentor lead and manage Developers I II III – Embedded Software Engineers based on project needs Identify and recommend appropriate tools (SW & HW) for the project. Developing utilizing various debug validation tools and/or methodologies to implement Development and validation plans Create share best practices and lessons learned with the team. Optimises efficiency cost and quality. Influence and improve customer satisfaction Set FAST goals for self/team and also provide feedback to FAST goals of team members Measures Of Outcomes Adherence to embedded design process and standards Quick turnaround on multiple alternative solutions determining the most suitable Number of technical issues uncovered during the execution of the project Number of review feedback post Software Lead II review based on project SLA Number of design and test defects post-delivery based on project SLA Quick turnaround on defect fixing for design and tests based on project SLA Adherence to testing methodologies and compliance process Adherence to project schedule / timelines Deploy Innovation techniques and publish white paper Team management and productivity improvement as per Project SLA. Requirement Outputs Expected: Lead requirement engineering; collaboration with internal and external customers to understand their needs Design Embedded design architecture/LLD and linking to requirements Develop Design the embedded SW and code as per design patterns coding standards templates and checklists. Develop automated tools or scripts for the validation environment. Test Analysis and testing of prototypes validate the designed software document the analysis and test results Document Create documentation for one's own work and contribute to creation of design HLD LLD/architecture for component/system software/ application diagnostics and test results Status Reporting Report status of tasks assigned; comply with project related reporting standards/process Quality Lead design reviews add value take responsibility for the design and overall quality of the embedded software Release Adhere to release management process for circuit simulation design schematics board files Compliance Adhere to embedded software design regulatory and test compliance Estimate Estimate time effort resource dependence for one's own work and for projects' work. Accurately define and document the technical side of the project schedule with estimates and identified risks Interface With Customer Clarify requirements and provide guidance to development team. Present design options to customers and conduct product demos Manage Project Manage delivery of embedded software and manage requirement understanding and effort estimation. Manage Team Set FAST goals and provide feedback. Understand aspirations of team members and provide guidance opportunities etc. Ensure team is engaged in project Manage Defects Perform defect RCA and mitigation. Identify defect trends and take proactive measures to improve quality Manage Knowledge Consume project related documents and specifications. Review the reusable documents created by the team Skill Examples Ability to create Embedded C Program Development for system level. Capability in creating and executing one or more of the following domains: Storage/connectivity/Media/graphics/boot/clusters/infotainment/ADAS Ability to do C++ programming (OOP) Assembly programming skills Ability to handle OS Scheduler Pre-emptive Round robin & Cooperative scheduling related work Ability to handle SW development in area of CAN Diagnostics Vehicle Functions etc. Aptitude in Networking protocols such as CAN LIN etc Ability to select right IoT & IO protocols as per problem statement. Ability to do Unit Testing (Tessy & RTRT) using appropriate Integration Testing Tools Ability to define and execute test cases with techniques (White Box and Black box) Ability in Closed loop LabCar INCA or similar tools Capacity to configure GDT framework. Ability to adhere to software quality standards (MISRA PCLINT QAC). Ability to debug using embedded tools Ability to do automation and configure Simulation Tools. Proactively ask for and offer help Ability to work under pressure determine dependencies risks facilitate planning and handle multiple tasks. Build confidence with customers by meeting deliverables in time with quality. Estimate effort time resources required for developing / debugging features / components Make decisions on appropriate of the Software / Hardware’s. Strong analytical and problem-solving abilities Knowledge Examples Knowledge on product development lifecycle Testing methodology and standards (Water Fall/ Agile) Knowledge in Test Automation scripting languages (e.g. Python Perl TCL) Knowledge with Wired (USB Ethernet PLC SCADA etherCAT Modbus RSxxx & Wireless technologies like NFC Bluetooth Wi-fi Zigbee etc. is a plus Understanding of automation frameworks (e.g. Hudson/Jenkin) Knowledge and knowhow on Diesel and Gasoline Engine Management Systems Knowledge of embedded algorithm integration on platform (Windows Linux and Android) Comprehension of ASPICE & ISO26262 process Knowledge in Pre-Silicon Verification environments for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge of MISRA 2004 and 2012 Coding guidelines (PC-lint LDRA & PRQA) Knowledge of CAN Tools: CANoe CANalyser & CAPL programming Knowledge of GDT framework internals Additional Comments Microcontroller ( STM32) Communication Protocols :- SPI, QSPI, I2C, UART, MODBUS Languages: C, C++, Java, Python Other:- Timer, PWM, Ethernet, RTC, TCP/IP. OS: Linux Proven experience in embedded firmware development, specifically with STM32 microcontrollers. Perform code reviews and maintain documentation for firmware development processes. Proficient in C/C++ programming languages. Experience with development tools such as STM32CubeIDE, IAR Embedded Workbench, or Keil. Experience with communication protocols (SPI, I2C, UART, Modbus etc.). Experience with Timer, PWM,ADC, QSPI, Flash, EEPROM, Uart RS285, Secure element, Ethernet. Experience in HMI interface. Experience in CyberSecurity, Mbedtls. Experience with real-time operating systems (RTOS) . Skills Microcontrollers,Spi,Embedded Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER Full Chip Low Power Design and Signoff Engineer Overview WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities MTS SILICON DESIGN ENGINEER ( Full Chip Low Power Design & Signoff Engineer ) The Role As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. The Person A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell’s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX Preferred Experience Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, Academic Credentials Bachelors or Master's degree in Computer/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Design verification plans and develop, maintain UVM testbench components. Gain a deep understanding of the design and testbench under your responsibility. Build UVM testbenches, including writing tests, sequences, checkers, scoreboards, and verification/coverage plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the improvement and evolution of GPU verification methodologies. Take ownership of coverage closure and provide verification metric reports. About You Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Experience in developing and maintaining verification components. Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies. Skilled in debugging and identifying root causes of issues. Effective communication of technical issues, both verbally and in writing. You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role We are looking for an adaptive, self-motivative EMIR engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The EMIR team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting - python/perl/tcl Must have knowledge of Physical Implementation (Synthesis and Place&Route) Effective communication Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+Yrs of exp. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Harman International is seeking highly driven and self-motivated RTL Design Engineers to join our cutting-edge semiconductor design team in Bangalore. This is a critical engineering role focused on synthesis, logic equivalence checking (LEC), and constraint development for high-performance digital IPs. You will be responsible for collaborating closely with architects, RTL developers, and other cross-functional teams to implement industry-standard design flows and methodologies. Responsibilities The ideal candidate is someone who has a strong understanding of physical design-aware synthesis, timing analysis, floor planning, and power optimization for advanced SoC and IP-level designs. Were looking for individuals who thrive in a fast-paced environment, are capable of taking full ownership of their deliverables, and can work independently with minimal Responsibilities : Collaborate with RTL designers and chip architects to implement synthesis, LEC (logic equivalence checks), and SDC (Synopsys Design Constraints) for NXPs digital IP designs. Own and drive physical-aware synthesis flows, including floorplanning and power/performance trade-off analysis for high-performance IPs. Perform timing and power analysis on the database (db), improve timing closure strategies, and provide actionable feedback to RTL and verification teams. Conduct timing signoff and static timing analysis (STA) using industry tools such as Primetime. Establish and maintain flow automation scripts for synthesis and LEC to support robust design delivery processes. Create and maintain design recipes to optimize timing, area, and power, ensuring delivery meets project milestones and design targets. Communicate effectively with cross-functional team members including verification, physical design, and program management to ensure smooth project execution. Take ownership as an individual contributor or lead engineer on specific IPs or subsystems, managing synthesis schedules and task breakdowns. Deliver weekly project status reports, capturing progress, challenges, and metrics around timing closure, synthesis QoR (Quality of Results), and tool flow efficiency. Desired Skills And Experience Experience : 3 to 12 years of relevant industry experience in RTL synthesis, LEC, and timing constraint development at the IP or SoC level. Strong understanding of synthesis flows, including setup from scratch and working with large-scale digital designs. Proficiency in using synthesis tools such as Synopsys Fusion Compiler, Design Compiler, or Cadence Genus. Hands-on experience with floorplanning, power optimization, and constraint development for advanced node designs (7nm/5nm/FinFET preferred). Solid understanding of timing analysis, multi-mode/multi-corner analysis, and power/timing closure methodologies. Practical knowledge of LEC tools like Conformal or Formality for equivalence checking. Familiarity with P&R (Place and Route) flow concepts and their influence on synthesis and timing constraints. Scripting expertise in TCL, Perl, and Python to automate design flows and reporting. Exposure to industry tools like Primetime, Innovus, and IC Compiler. Ability to work independently or as a team lead with minimal supervision and clear accountability for deliverables. Strong documentation and communication skills to maintain flow manuals and collaborate across geographically distributed teams. Preferred Qualifications Bachelor's or Masters degree in Electronics and Communication Engineering, VLSI Design, Computer Engineering, or a related field. Exposure to advanced SoC design and verification environments. Experience working in product companies or semiconductor IDMs will be considered a plus. (ref:hirist.tech) Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As member of the physical design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design & Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What We're Looking For BSEE or MS with 12+ years of experience running industry standard EDA tools for PnR & signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Job Description As a Staff Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM IP. Analyze design timing, area and power to help improve the quality of ARM IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl and R. “Nice To Have” Skills and Experience Knowledge around Arm based SoCs! Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python and Ruby. Experience with low power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

Company Description Pushing the Edge VANTIVA, headquartered in Paris, France and formerly known as Technicolor, is a global technology leader in designing, developing and supplying innovative products and solutions that connect consumers around the world to the content and services they love – whether at home, at work or in other smart spaces. VANTIVA has also earned a solid reputation for optimizing supply chain performance by leveraging its decades-long expertise in high-precision manufacturing, logistics, fulfillment and distribution. With operations throughout the Americas, Asia Pacific and EMEA, VANTIVA is recognized as a strategic partner by leading firms across various vertical industries, including network service providers, software companies and video game creators for over 25 years. Our relationships with the film and entertainment industry goes back over 100 years by providing end-to-end solutions for our clients. VANTIVA is committed to the highest standards of corporate social responsibility and sustainability across all aspects of their operations. For more information, please visit www.vantiva.com and follow us on LinkedIn and Twitter. Job Description 6 - 8 years of experience in CPE testing, with a focus on functional testing, performance, and reliability. Strong understanding of Oops concept & Hands on in Java programming | Selenium knowledge is strong plus. Proficient in debugging and troubleshooting complex issues with solid understanding of networking technologies like, CMTS, OLT, 5G and DSLAM. Strong believer in creating impact thru Test automation with hands on experience in Java/Selenium | Python scripting experience is a plus Hands-on experience in WiFi, Ethernet and voice testing is a strong plus. Excellent stake holding & communication skills (written & verbal). Key Responsibilities Perform WIFI, Ethernet and voice testing, in the RDK-B or OpenWRT based firmware. Test and validate functionality of the broadband devices with the core components like CMTS/OLT/DSLAM/5G equipment. Work with CWMP suite of protocol for remote management and configuration of customer-premises equipment (CPE). Perform with ‘Intent to break’ approach in testing, Strong analytical skills with curiosity to triage/debug for root cause analysis/troubleshooting on issues uncovered, and intent work with the engineering team to resolve them. Ability to parallel tasking under tight timeline, result driven approach with adequate contingency planning Stay updated with the latest industry trends and technologies to continuously improve testing methodologies. Qualifications Key Skills: Strong knowledge in WiFi testing (all standard, preferably 802.11BE), DOCSIS or GPON/XGS-PON, TR-069 protocol, and Python/Java automation. Handson Expertise in throughput testing of WLAN solution, specifically 802.11be with MLO technology Good understanding of OpenWRT, and RDK platforms. Proficiency in Easy Mesh R4,5,6 standards and hands on experience on testing various network topologies Familiar with TR69/USP, Routing, UPnP, Firewall, content sharing, NAT, TR398, TR181 Routing protocols will be an added advantage Hands on expertise with any of the testing tools like STC, IXIA IP Performance testing, AirPcaP with Wireshark, ixCharoit, CD Router, Octoscope etc., Java Programming experience along with Scripting knowledge in either Selenium / Python for test automation. Good understanding of network testing procedures and methodologies. Additional Skills/Experiences Experience in Automatics or TCL programming is welcome advantage. Strong expertise in networking protocols and concepts, including TCP/IP, Ethernet, and Wi-Fi standards. Additional Information Vantiva is an EOE/Veterans/Disabled/LGBT employer : Vantiva is proud to be an equal opportunity workplace. We will consider all qualified applicants for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other basis protected by applicable law. Our most important asset is our People Vantiva’s success greatly relies on our people’s energy, motivation, and talent. We are dedicated to cultivating a workforce that embraces and celebrates diversity as we believe our differences drive our creativity, and innovation. We are proactive in supporting equality and maintaining an inclusive work environment, developing, and enhancing career opportunities for all. If you require a reasonable accommodation at any step of the application process, please let us know by answering the dedicated question in this application form. Our most important asset is our People Vantiva’s success greatly relies on our people’s energy, motivation, and talent. We are dedicated to cultivating a workforce that embraces and celebrates diversity as we believe our differences drive our creativity, and innovation. We are proactive in supporting equality and maintaining an inclusive work environment, developing, and enhancing career opportunities for all. If you require a reasonable accommodation at any step of the application process, please let us know by answering the dedicated question in this application form. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 2 to 5 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Grow with us About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor’s degree in Electrical or Computer Engineering or equivalent. Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 768495

AV-273335 Ahmedabad,Gujarāt,India Full-time Permanent 48 eCommerce Solutions Blue Dart Express Limited Job Title Executive - TCL Operations Function Operations Reporting to Manager - TCL Operations 1. Purpose Support all activities relating to operations of Temperature Control Logistics (TCL) shipments across the organization 2. Key Responsibilities Responsibilities Operational Support in Formulation and driving the strategy for Temperature Control Logistics (TCL) operations across the organization Monitor and control all TCL packaging and storing related costs Support in designing and developing the policies, procedures and Standard Operating Procedures (SOPs) for TCL operations Support the planning, monitoring and controlling of all aspects of TCL shipments, to deliver customized solutions and improvements in service and cost performance Responsible for management of day to day operations of TCL shipments, across all locations as per SOPs Monitor the customer requirements for TCL to ensure, they are completed and delivered on time and within the correct temperature range Drive appropriate handling of TCL shipments as per customer specifications (temperature) through measures including use of appropriate packaging, monitoring of package temperatures, sending pre-alerts to locations for TCL shipments, etc. Oversee coordination with customers, regional sales teams, regional operations teams and any other relevant department to ensure delivery as per customer requirements Responsible for maintenance of all packaging inventory as per SOPs Drive appropriate handling and maintenance of freezers/ cold rooms and all TCL inventory and equipments including gel packs, temperature loggers, etc. Play an active role in the identification and empanelment of vendors for supply of dry ice as per organization requirements Play an active role in the development and sourcing of packaging solutions for TCL shipments and liaison with vendors (including international vendors) for the same Support in conduction of regular trainings of TCL operations staff on aspects related to preservation, handling, storing, and maintenance of TCL shipments Monitor the overall service quality of TCL operations and take necessary corrective action (as required) in coordination with the relevant departments 3. Key Result Areas and Key Performance Indicators S. No Key Result Areas Key Performance Indicators 1. Optimization of operating costs % reduction in overall Operating Costs (i.e. OCPK, OCPM) for TCL shipments 2. Reach Enhancement Number of new Pin Codes added for TCL Shipments 3. Drive overall operational performance for TCL shipments Overall service quality for TCL Shipments in terms of Net Service Levels (NSLs) Achievement of target NPS Scores for TCL Shipments % shipments rejected by customer on account of incorrect temperature during transit (data obtained from time loggers) 4. Ensure setup of effective operations processes and policies for TCL product Design and implement processes and SOPs for TCL as per plan Support in new product development for TCL( from an operational point of view) 5. Drive Employee Capability Building for Operations Design of operations training programmes for TCL operations teams as per timelines Conduct/ delivery of TCL operations training programs as per plan % coverage of TCL operations staff (as per plan) in terms of TCL training programmes

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply! About The Role We are looking for an experienced Principal Physical Design Engineer (CAD) to join our small but growing Processor Design group, advancing the art of high performance implementation and physical design. deal candidates will develop and maintain physical design flows for high performance designs. What You’ll Achieve Develop and support innovative physical design methodology and custom CAD Work closely with implementation and physical design (PD) team Debugging flow issues Running multiple test designs through flow on latest technologies to determine impact on technology changes to area, power and timing Automating new flow practices for general use in the design community About You M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in physical design CAD flow including synthesis, place & route, and floor planning Preferred - power distribution, static timing analysis and physical design verification Experience in hierarchical P&R and flow development. Experience with all aspects of PD including floorplanning, power-distribution, pad ring construction, placement, CTS, and routing. Understand hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.) Strong TCL/Perl/Makefile scripting knowledge. Experience in developing complex algorithms, managing, and regressing P&R flows. Familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies. Good communication and problem-solving skills What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

JOB description 4-14years Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience. Show more Show less

Job Details: : In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII. You will be part of ACE Group, in the P-Core design team driving Intels latest CPUs in the latest process technology. Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design.Static timing analysis. Power OptimizationDesign Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute Scale and Performance engineer shall be responsible for validating feature scale and performance, run manual or automation S&P tests against all supported features developed across Ciena's Routing and Switching platform portfolio. Work involves scale and performance validation along robustness test and automate test plans to verify product capabilities. Execution of feature scale test-plans, test bed design, test topologies, Test Automation & test Executions. Set up complex test beds based on Project requirements. Assist development engineers in product defect diagnosis/debugging and verification of fixes. Day-to-day activities include planning, designing, automating, and validating tests around scale, performance, longevity and robustness tests across all supported features or feature combinations (Uni-D and Multi-D) to validate system behavior at limit and endurance. Develop test-plans, plan and design test-topologies and test methodologies with optimal resource usage. Prepare/Automate robust, quality, S&P scripts with robustness and longevity also in perspective with optimal CPU and memory measurement reading mechanisms, and feature/systemic performance measurement mechanisms. Use JIRA to file defects following proper template, and all logs/debug command output/traffic flow footprint, etc. relevant to the problem description. Assist development engineers in product defect diagnosis/debugging/reproduction and verification of fixes. Execution of test cases and reporting test results with artifacts using Test Rail Work closely with engineers across teams/geographies to ensure quality for the features. Position requires troubleshooting and problem-solving skills Understand Software Development Life Cycle. Conducts Knowledge Sharing Sessions (Desirable): Basic to moderate topics, including specific product feature or functional areas related the assigned features. Able to manage feature and schedule churns with minimal guidance. Contribute to team deliverable through involvement in agile scrum development sprints. The Must Haves 5-8 years of experience in telecommunication and testing. Experience with Python/Tcl/Expect is a must. Fluency and experience in data communication systems, networking, Ethernet switches and Routers. Hands-on experience with L2/L3 topologies. Strong testing experience in some of the Layer-2 protocols like Ethernet Switching, VLANs, G.8032, CFM,Y.1731,BFD,VPLS,VPWS,QoS and L3 protocols like BGP, IS-IS, OSPF Working experience in areas like EVPN, L2VPN,L3VPN and in transports like MPLS,SR,LDP,RSVP Experience with traffic generators such as Ixia, Spirent. The Good To Haves Good knowledge of network design and deployment scenarios in Carrier/Metro Ethernet Space is plus. Netconf/GNMI/Telemetry exposure is an added advantage. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less