Physical Design Engineer Lattice Semiconductor

12.0 - 16.0 years

0 Lacs

pune, maharashtra

On-site

Role Overview: As a Sr. Staff Physical Design Engineer at Lattice Semiconductor in Pune, India, you will be part of the HW design team focusing on IP design and full chip integration. Your role involves implementing and leading the RTL to GDSII flow for complex designs, including tasks such as place & route, CTS, routing, floorplanning, powerplanning, and physical signoff. You will also be responsible for driving efficiency and quality in physical design flow, collaborating with internal and external teams, and leveraging scripting knowledge to enhance design efficiency. Key Responsibilities: - Implement and lead the RTL to GDSII flow for complex designs - Work on various aspects of physical...

Posted 3 weeks ago

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Strategic / Leadership Role Advanced Micro Devices, Inc

20.0 - 24.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: You will be working as a Fellow Silicon Design Engineer at AMD to develop world-class Server products. Your main responsibility will be to define and drive PPA uplift methodologies, develop power optimization methodology for Physical Design Implementation, define PVT corners and frequency targets for next-generation Servers, and have a deep knowledge of micro-architecture, power optimization methodologies, and timing closure. You are expected to have very strong problem-solving skills, broad experience in methodology, and a self-motivated work ethic to provide a cohesive technical vision for PPA improvement methodology. Key Responsibilities: - Define and drive PPA uplift metho...

Posted 1 month ago

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Senior Asic Engineer Acesoft Labs

5.0 - 10.0 years

5 - 14 Lacs

hyderabad

Work from Office

We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes. Responsibilities: Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC. Manage hierarchical physical verification and signoff closures. Develop and implement advanced UVM verification environments for IP and full-chip verification. Verify ...

Posted 1 month ago

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